SNAU297 July   2025 LMK5B12212 , LMK5C22212A

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Using LMK5B12212EVM to evaluate LMK5C22212A
  6. 2Hardware
    1. 2.1 Test Equipment Recommended
    2. 2.2 LMK5B12212EVM Default Settings
    3. 2.3 EVM Quick Start
  7. 3Software
    1. 3.1 Getting Started With TICS Pro
    2. 3.2 Programming the LMK5B12212
    3. 3.3 Configuring TICS Pro
      1. 3.3.1  Using the Start Page
        1. 3.3.1.1 Step 1
        2. 3.3.1.2 Step 2
        3. 3.3.1.3 Step 3
        4. 3.3.1.4 Step 4
        5. 3.3.1.5 Step 5
        6. 3.3.1.6 Step 6
        7. 3.3.1.7 Step 7
        8. 3.3.1.8 Step 8
      2. 3.3.2  Using the Status Page
      3. 3.3.3  Using the Input Page
        1. 3.3.3.1 Cascaded Configurations
          1. 3.3.3.1.1 Cascade VCO to APLL Reference
      4. 3.3.4  Using APLLx Pages
        1. 3.3.4.1 APLL DCO
      5. 3.3.5  Using the DPLLx Page
        1. 3.3.5.1 DPLL DCO
      6. 3.3.6  Using the Validation Page
      7. 3.3.7  Using the GPIO Page
        1. 3.3.7.1 SYNC/SYSREF/1-PPS Page
      8. 3.3.8  Using the Outputs Page
      9. 3.3.9  EEPROM Page
      10. 3.3.10 Design Report Page
  8. 4EVM Configuration
    1. 4.1 Evaluation Setup
      1. 4.1.1 Power Supply
      2. 4.1.2 Logic Inputs and Outputs
      3. 4.1.3 Switching Between I2C and SPI
      4. 4.1.4 Generating SYSREF Request
      5. 4.1.5 XO Input
        1. 4.1.5.1 48MHz TCXO (Default)
        2. 4.1.5.2 External Clock Input
        3. 4.1.5.3 Additional XO Input Options
        4. 4.1.5.4 APLL Reference Options
      6. 4.1.6 Reference Clock Inputs
      7. 4.1.7 Clock Outputs
      8. 4.1.8 Status Outputs and LEDS
      9. 4.1.9 Requirements for Making Measurements
    2. 4.2 Typical Phase Noise Characteristics
  9. 5Hardware Design Files
    1. 5.1 Schematics
      1. 5.1.1  Power Supply Schematic
      2. 5.1.2  Alternative Power Supply Schematic
      3. 5.1.3  Power Distribution Schematic
      4. 5.1.4  LMK5B12212 and Input References IN0 to IN1 Schematic
      5. 5.1.5  Clock Outputs OUT0 to OUT3 Schematic
      6. 5.1.6  Clock Outputs OUT4 to OUT7 Schematic
      7. 5.1.7  Clock Outputs OUT8 to OUT11 Schematic
      8. 5.1.8  XO Schematic
      9. 5.1.9  Logic I/O Interfaces Schematic
      10. 5.1.10 USB2ANY Schematic
    2. 5.2 PCB Layouts
      1. 5.2.1 Layout Guidelines
      2. 5.2.2 Layout Example
      3. 5.2.3 Thermal Reliability
    3. 5.3 Bill of Materials (BOM)
      1. 5.3.1 Loop Filter and Vibration Nonsensitive Capacitors

1.1 Introduction

The LMK5B12212EVM is an evaluation module for the LMK5B12212 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping. The LMK5B12212 integrates two Analog PLLs (APLL) and one Digital PLL (DPLL) with programmable loop bandwidth. The EVM includes SMA connectors for clock inputs, optional off-board APLL reference input, and clock outputs to interface the device with 50Ω test equipment. The onboard TCXO allows the LMK5B12212 to be evaluated in free-running, locked, or holdover mode of operation. The EVM can be configured through the onboard USB microcontroller (MCU) interface using a PC with TI's TICS Pro software graphical user interface (GUI). TICS Pro can be used to program the LMK5B12212 registers.