SNAU318 June   2025 LMX1205

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Jumper Information
    3. 2.3 Multiplier Lock Detect Jumper
    4. 2.4 Setup
      1. 2.4.1 Evaluation Setup Requirement
      2. 2.4.2 Connection Diagram
    5. 2.5 Power Requirements
    6. 2.6 Reference Clock
    7. 2.7 Output Connections
    8. 2.8 Test Points
  7. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  8. 4Implementation Results
    1. 4.1 Buffer Mode
    2. 4.2 Multiplier and Divider Modes
    3. 4.3 Logic Clock
    4. 4.4 Programmable Delay
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Trademarks

Description

The LMX1205 multisite evaluation module (EVM) is designed to evaluate the cascaded performance of the LMX1205. The LMX1205 is a four-output, ultra-low, additive jitter radio-frequency (RF) buffer, divider and multiplier. The device buffers RF frequencies up to 12.8GHz, multiplies RF outputs from 6.4GHz up to 12.8GHz, and divides outputs by up to 12.8GHz. This board consists of three LMX1205 devices (one primary device that drives two secondary devices) and vertical header to connect IDC cable for USB2ANY interface. The multisite board also emphasizes features such as a multipart clock synchronization using sync, programmable delay, device-to-device SYSREF interface (single/differential ended, DC/AC coupled mode). Maximum device performance is extractable from the two secondary devices, the output of primary LMX1205 drives the clock and SYSREF inputs.