SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

4.4 1080p60 with External Clock Example Configuration

This example configures the pattern generator for a 1920x1080 60Hz output using an external PCLK reference frequency applied at the serializer input. This example can only be used with 94x devices in dual FPD Link mode:

Table 4-2 1080p60 with External Clock Example
ParameterValueUnits
Pixel Clock (Applied Externally)148.5MHz
Total Horizontal Width2200pixels
Total Vertical Height1125pixels
Active Horizontal Width1920pixels
Active Vertical Height1080pixels
Horizontal Sync Width44pixels
Vertical Sync Width5pixels
Horizontal Back Porch148pixels
Vertical Back Porch36pixels
Horizontal Sync PolarityPositive-
Vertical Sync PolarityPositive-

Configuration Sequence

  1. Set Pixel Clock and Active Frame Size. Active H Width: 1920 (dec) = 0111 1000 0000 (bin), Active V Height: 1080 (dec) -> 0100 0011 1000 (bin)
    1. Write 0x07 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGAFS1, then write 0x80 (Table 3-13) to address 0x67 PGID (Table 3-2) to set desired Active Horizontal Width.
    2. Write 0x08 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGAFS2, then write 0x87 (Table 3-14) to address 0x67 PGID (Table 3-2) to set desired Active Vertical and Horizontal Widths.
    3. Write 0x09 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGAFS3, then write 0x43 (Table 3-15) to address 0x67 PGID (Table 3-2) to set desired Active Vertical Width.
  2. Set Total Frame Size. Total H Width: 2200 (dec) -> 1000 1001 1000 (bin), Total V Width: 1125 (dec) -> 0100 0110 0101 (bin)
    1. Write 0x04 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGTFS1, then write 0x98 (Table 3-10) to 0x67 PGID (Table 3-2) to set desired Total Horizontal Width.
    2. Write 0x05 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGTFS2, then write 0x58 (Table 3-14) to address 0x67 PGID (Table 3-2) to set desired Total Vertical and Horizontal Widths.
    3. Write 0x06 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGTFS3, then write 0x46 (Table 3-12) to address 0x67 PGID (Table 3-2) to set desired Total Vertical Width.
  3. Set Back Porch. H Back Porch: 148 (dec) 1001 0100 (bin), V Back Porch: 36 (dec) lines 0010 0100 (bin)
    1. Write 0x0C (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGHBP, then write 0x94 (Table 3-18) to address 0x67 PGID (Table 3-2) to set desired Horizontal Back Porch Width.
    2. Write 0x0D (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGVBP, then write 0x24 (Table 3-19) to address 0x67 PGID (Table 3-2) to set desired Vertical Back Porch Width.
  4. Set Sync Width. H Sync Width: 44 (dec) pixels 0010 1100 (bin), V Sync Width: 5 (dec) lines 0101 (bin)
    1. Write 0x0A (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGHSW, then write 0x2C (Table 3-18) to address 0x67 PGID (Table 3-2) to set desired Horizontal Sync Width.
    2. Write 0x0B (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGVSW, then write 0x05 (Table 3-19) to address 0x67 PGID (Table 3-2) to set desired Vertical Sync Width.
  5. Set Sync Polarities.
    1. Write 0x0E (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PBSC, then write 0x00 (Table 3-18) to address 0x67 PGID (Table 3-2) to set desired horizontal and vertical sync polarities to "Positive".
  6. Enable Pattern Generation
    1. Write 0x0C to address 0x65 PGCFG (Table 3-2) to set external clock and internal PATGEN timing.
    2. Write 0x05 to address 0x64 PGCTL (Table 3-2) to enable PATGEN with color bars.