SNLA267A March   2019  – June 2019 DS90UB953-Q1 , DS90UB954-Q1 , DS90UB960-Q1

 

  1.   How to Design a FPD-Link III System Using DS90UB953-Q1 and DS90UB954-Q1
    1.     Trademarks
    2. 1 Overview
      1. 1.1 System Level Functionality
    3. 2 Basic Design Rules
      1. 2.1 IDX and MODE Pin Verification
        1. 2.1.1 REF Clock, CLK IN, AON and Frequency Selection
          1. 2.1.1.1 Synchronous Mode
          2. 2.1.1.2 Non-Synchronous CLK_IN Mode
          3. 2.1.1.3 Non-Synchronous AON Mode
          4. 2.1.1.4 CSI Throughput
          5. 2.1.1.5 Clocking and Frequency Selection Example
      2. 2.2 Successful I2C Communication With 953 and 954
        1. 2.2.1 Aliasing
        2. 2.2.2 Port Selection on 954
      3. 2.3 I2C Passthrough Verification
      4. 2.4 Basic Diagnostic and Error Registers
    4. 3 Designing the Link Between SER and DES
      1. 3.1 Back Channel Configuration
      2. 3.2 BIST
        1. 3.2.1 BIST Configuration and Status
        2. 3.2.2 BIST Procedure
        3. 3.2.3 List of Registers Used in BIST Script
      3. 3.3 AEQ
      4. 3.4 CML Out
    5. 4 Designing Link Between SER and Image Sensor
      1. 4.1 Sensor Initialization Using SER GPIOs
      2. 4.2 CLKOUT
    6. 5 Designing Link Between DES and ISP
      1. 5.1 Frame Sync
        1. 5.1.1 Using SER GPIOs From the DES
        2. 5.1.2 Internal and External Frame Sync Configuration
        3. 5.1.3 Tables for Using GPIOs and Frame Sync
      2. 5.2 Port Forwarding
      3. 5.3 Pattern Generation
        1. 5.3.1 Accessing Indirect Registers
        2. 5.3.2 Pattern Generation From DES to ISP and SER to DES
    7. 6 Hardware Design
      1. 6.1 Basic I2C Connectors
        1. 6.1.1 I2C Pullups for SDA and SCL
      2. 6.2 AC Capacitor on FPD3 Link
      3. 6.3 Capacitance Used in Loop Filter
      4. 6.4 Critical Signal Routing
      5. 6.5 Time Domain Reflection
      6. 6.6 Return Loss and Insertion Loss
      7. 6.7 Power-over-Coax (PoC)
      8. 6.8 Voltage and Temperature Sensing
    8. 7 Appendix
      1. 7.1 Scripts
        1. 7.1.1  BIST Script
        2. 7.1.2  Example Sensor Initialization Script
        3. 7.1.3  CSI Enable and Port Forwarding Script
        4. 7.1.4  Enabling CMLOUT FPD3 RX Port 0 on 954
        5. 7.1.5  Remote Enabled SER GPIO Toggle Script
        6. 7.1.6  Local SER GPIO Toggle Script
        7. 7.1.7  Internal FrameSync on 953 GPIO1
        8. 7.1.8  External FrameSync on 953 GPIO0
        9. 7.1.9  SER GPIOs as Inputs and Output to DES GPIO
        10. 7.1.10 Pattern Generation on the 953 Script
        11. 7.1.11 Pattern Generation on the 954 Script
        12. 7.1.12 Monitor Errors for Predetermined Time Script
        13. 7.1.13 954 and 953 CSI Register Check Script
        14. 7.1.14 Time Till Lock Script on 953
      2. 7.2 Acknowledgments
  2.   Revision History

2.1 IDX and MODE Pin Verification

Each IDX and Mode pin contains a voltage divider to the respective IDX and Mode pins on the 953 and 954. The IDX and Mode pins read the voltage on the pin, and the internal comparators decide which IDX or Mode is assigned to each device. As a result, the required voltage supply and the ratio of the resistor divider are used to set the IDX and Mode pins.

  1. Ensure commands refer to correct I2C addresses by checking the IDX pin.
    1. The IDX pin configures the control interface to one of many possible device addresses used in I2C communication. Usually for 1.8-V or 3.3-V referenced I2C I/O voltage, a pullup resistor and a pulldown resistor is used to set the appropriate voltage on the IDX input pin of both devices.
    2. The IDX resistor divider must be referred to Pin #25 on the 953 and Pin #35 on the 954. Tables that hold appropriate resistor values for setting IDX are shown below.
    3. For example the 953 can have an open pullup resistor, a 40.2-kΩ pulldown resistor, and an I2C supply of 1.8 V to achieve a device ID of 0x30. This is shown in Table 1.

    2. Table 1. Serial Control Bus Addresses for IDX on the 953

    IDX VTARGET VOLTAGE RANGE VIDX TARGET VOLTAGE SUGGESTED STRAP RESISTORS (1% TOL) I2C 8-BIT ADDRESS 12C 7-BIT ADDRESS I2C I/O VOLTAGE
    RATIO MIN RATIO TYP RATIO MAX VVDD = 1.8 V RHIGH (kΩ) RLOW (kΩ)
    1 0.000 0.00 0.131 0.000 Open 40.2 0x30 0x18 1.8 V
    2 0.178 0.214 0.256 0.385 180 47.5 0x32 0x19 1.8 V
    3 0.537 0.564 0.591 1.015 82.5 102 0x30 0x18 3.3 V
    4 0.652 0.679 0.706 1.223 68.1 137 0x32 0x19 3.3 V

    Table 2. Serial Control Bus Addresses for IDX on the 954

    NO. VIDX VOLTAGE RANGE VIDX TARGET VOLTAGE SUGGESTED STRAP RESISTORS (1% TOL) PRIMARY ASSIGNED I2C ADDRESS
    VMIN VTYP VMAX (V); VDD1P8 = 1.8 V RHIGH (KΩ) RLOW (KΩ) 7-BIT 8-BIT
    0 0 0 0.131 × V(VDD18) 0 OPEN 10.0 0x30 0x30
    1 0.179 × V(VDD18) 0.213 × V(VDD18) 0.247 × V(VDD18) 0.374 88.7 23.2 0x32 0x32
    2 0.296 × V(VDD18) 0.330 × V(VDD18) 0.362 × V(VDD18) 0.582 75.0 35.7 0x34 0x34
    3 0.412 × V(VDD18) 0.443 × V(VDD18) 0.474 × V(VDD18) 0.792 71.5 56.2 0x36 0x36
    4 0.525 × V(VDD18) 0.559 × V(VDD18) 0.592 × V(VDD18) 0.995 78.7 97.6 0x38 0x38
    5 0.642 × V(VDD18) 0.673 × V(VDD18) 0.704 × V(VDD18) 1.202 39.2 78.7 0x3A 0x3A
    6 0.761 × V(VDD18) 0.792 × V(VDD18) 0.823 × V(VDD18) 1.420 25.5 95.3 0x3C 0x3C
    7 0.876 × V(VDD18) V(VDD18) V(VDD18) 1.8 10.0 OPEN 0x3D 0x3D
  2. Ensure devices are in correct mode by checking the MODE.
    1. As shown in Table 3, the DS90UB953-Q1 can operate in one of many different modes that define the clocking the 953. The default mode is selected by the bias voltage applied to the MODE pin (21) during power up. To set this voltage, a potential divider between VDD and GND is used to apply the appropriate bias. TI recommends that this potential divider should be referenced to the potential on the VDDD pin (25). After power up, the MODE can be read or changed through register access. On the 953, register 0x03 controls MODE_SEL.
    2. As shown in Table 4, the DS90UB954-Q1 can operate in many different modes that define the expected imager data format. Mode is defined on power up through a voltage divider to the Mode pin (37). While the 954 can be placed in different modes, the only compatible mode with the 953 is the CSI-2 Mode. After power up, the mode can be controlled by the first 2 bits of the PORT_CONFIG register with address of 0x6D.
    3. The most common deserializer mode configuration for a 954 and 953 system is to use a CSI-2 port and a coaxial cable between the devices. As a result, a pullup resistor of 78.7 kΩ, a pulldown resistor of 97.6 kΩ, and 1.8 V for VDD are used.

    3. Table 3. DS90UB953-Q1 Strap Configuration Mode Select

    MODE NO. VTARGET VOLTAGE RANGE VTARGET STRAP VOLTAGE SUGGESTED STRAP RESISTORS (1% TOL) DESCRIPTION
    RATIO MIN RATIO TYP RATIO MAX (V); V(VDD) = 1.8 V RHIGH (kΩ) RLOW (kΩ)
    1 0.000 0.000 0.133 0.000 OPEN 10 CSI-2 Synchronous mode – FPD-Link III Clock reference derived from deserializer 2
    2 0.288 × V(VDD) 0.325 × V(VDD) 0.367 × V(VDD) 0.586 75 35.7 CSI-2 Non-synchronous CLK_IN – FPD-Link III Clock reference derived from external clock reference input CLK_IN pin
    3 0.412 × V(VDD) 0.443 × V(VDD) 0.474 × V(VDD) 0.792 71.5 56.2 CSI-2 Non-synchronous AON – FPD-Link III Clock reference derived from internal AON clock.

    Table 4. DS90UB954-Q1 Strap Configuration Mode Select

    MODE NO. VTARGET VOLTAGE RANGE VTARGET STRAP VOLTAGE SUGGESTED STRAP RESISTORS (1% TOL) RX MODE
    VMIN VTYPTARGET VMAX (V); VDD1P8 = 1.8 V RHIGH (kΩ) RLOW (kΩ)
    0 0 0 0.131 × VDD18 0 OPEN 10 CSI
    1 0.525 × VDD18 0.559 × VDD18 0.592 × VDD18 0.995 78.7 97.6 CSI