SNLA308A April   2019  – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Superframe Requirements
    1. 2.1 Left/Right 3D Format
    2. 2.2 Alternate Line 3D Format
    3. 2.3 Alternate Pixel 3D Format
  4. 3 Video Processing Status Monitoring
    1. 3.1 VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
  5. 4 Superframe Splitting
  6. 5 Frame Cropping
    1. 5.1 Cropping Control Registers
      1. 5.1.1 CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
      2. 5.1.2 CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
      3. 5.1.3 CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
      4. 5.1.4 CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
      5. 5.1.5 CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
      6. 5.1.6 CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
      7. 5.1.7 CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
      8. 5.1.8 CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
    2. 5.2 Cropping Options
  7. 6 Splitter Mode Pixel Clocks
    1. 6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
    2. 6.2 SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
  8. 7 Programming Example
  9. 8 Summary
  10. 9 References
  11. 10Handling Interrupts With the DS90Ux941AS-Q1
    1. 10.1 Interrupt Control and Status (INTB and REM_INTB Pin)
    2. 10.2 Handling Interrupts in Splitter Mode Using Remote Interrupt Pin (REM_INTB)
    3. 10.3 REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
  12. 11High-Speed GPIO Operation in Splitter Mode
    1. 11.1 Introduction
    2. 11.2 High-Speed Control Configuration
      1. 11.2.1 DES_CAP1 Registers (Address = 20h)
      2. 11.2.2 DES_CAP2 Registers (Address = 21h)
    3. 11.3 Back Channel Frequency Configuration
    4. 11.4 Splitter Mode GPIO
    5. 11.5 GPIO_0_Config Register (Address = Dh) [reset = 20h]
    6. 11.6 GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
    7. 11.7 GPIO_3_Config Register (Address = Fh) [reset = 0h]
  13.   Revision History

5 Frame Cropping

Asymmetric splitting of frames can be accomplished by cropping the resultant output images. The input video requirements are the same as those for the symmetric splitting. The superframe must include two identical size images. Those images are cropped in both the horizontal and vertical dimensions to produce reduced size images. Note that the clock frequency remains half the frequency of the superframe. In addition, the horizontal and vertical blanking intervals are increased by the magnitude of the cropping.

Figure 5-1 shows one superframe stream input on the DSI0 (DSI1 also possible) that is split into two different video resolutions. When the superframe is received, it is reformatted to the alternate pixels 3D format before the superframe is split into two images. The cropping function is then performed on either one or both of the resultant images to get the desired resolutions before the images are forwarded to the compatible deserializers and attached displays.

GUID-20201027-CA0I-ZFG8-N9K6-40NFXTPNSCXM-low.gifFigure 5-1 Asymmetric Splitting With Cropping

The engineer can enable image cropping on each image to handle asymmetric splitting. To crop each image, the engineer must program the horizontal and vertical dimensions in the registers described in Section 5.1. The origin of the frame begins at the start of the active video as shown in the figure Figure 5-2 below. Typically, for asymmetric split, the difference between the active videos in both horizontal and vertical dimensions is added to the front porch of the smaller video. However, in the SuperFrame image, the resultant image can be offset such that the front porch and back porch can have different values. Figure 5-2 shows the relation between the resultant crop image and the blanking parameters.

GUID-21A2FFE1-8466-4EB1-A4E5-5EB08112C7E1-low.gifFigure 5-2 Cropping Example