SNLA411 October   2022 DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TC813R-Q1 , DP83TC813S-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
    1. 1.1 System Block Diagram
    2. 1.2 Terminology
  4. 2 TC10 Pin Descriptions
  5. 3 Primary Functions of the PHY
    1. 3.1 Transition from Sleep to Wake-up mode
      1. 3.1.1 Local Wake Detection
      2. 3.1.2 WUP Transmission and Reception
    2. 3.2 Wake Forwarding
    3. 3.3 Transition to Sleep - Sleep Negotiation
      1. 3.3.1 Sleep Ack
      2. 3.3.2 Sleep Request
      3. 3.3.3 Sleep Silent
      4. 3.3.4 Sleep Fail
      5. 3.3.5 Sleep
      6. 3.3.6 Normal State
      7. 3.3.7 Other Transitions
        1. 3.3.7.1 Forced Sleep
        2. 3.3.7.2 Activity during Sleep Negotiation
        3. 3.3.7.3 Link Down during Sleep Negotiation
        4. 3.3.7.4 Sleep Silent to Standby
  6. 4 Relevant Registers
  7. 5 Power Supply Recommendation
    1. 5.1 Core Supply Network Recommendation
    2. 5.2 Networks with Shared Core Supplies
  8. 6 Sequence of Events and Timing
    1. 6.1 Local Wake Timing
    2. 6.2 Remote Wake Timing
    3. 6.3 Successful Sleep Negotiation Timing
    4. 6.4 Sleep Abort Timing
    5. 6.5 WUR Timing
  9. 7 Ethernet Network Wake-up
  10. 8 Configuration for non-TC10 Applications
  11. 9 Additional Features
    1. 9.1 WUR Initiation Through WAKE Pin
    2. 9.2 Programmable Wake-Forward Pulse Width
  12. 10Conclusion

4 Relevant Registers

This section explains the relevant register fields used in TC10 implementation. Other fields sharing the same register address and are not relevant to TC10 are excluded from this section. The complete register list is available in the data sheet.

Table 4-1 Register Description
Register Name Register Address Bit Field Name Access Type Default Value Description
TC10_ABORT_REG 0x001B 0 cfg_sleep_abort R/W 0x0 Sleep Abort

1b = Abort sleep when the PHY is in Sleep Ack state
1 cfg_tc10_abort_gpio_en R/W 0x0 Use LED_1 pin to abort sleep (CLKOUT if RX_D3 strap is set to high)

1b = Use LED_1 pin to abort sleep (drive high for abort)
LPS_CFG2 0x018B 1 cfg_lps_sleep_en R/W 0x1 Transition to sleep mode after Sleep negotiation:

0b = Transition to Standby mode

1b = Transition to Sleep mode
6 cfg_auto_mode_en R/W 0x01 Autonomous Mode enable (Default value dependent on Strap):

0b = Manual Mode

1b = Autonomous Mode

Note: This bit is auto cleared after link-up.
8 cfg_tc10_dis_bond_pad_bypass R/W 0x0 TC10 State Machine Disable:

0b = Enable

1b = Disable
11 cfg_stop_sleep_neg_on_activity R/W 0x1 Stop Sleep Negotiation on Activity:

0b = Continue Sleep Negotiation even if activity (packet transfer) is present

1b = Stop Sleep Negotiation on Activity
12 cfg_stop_sleep_neg_on_no_send_n R/W 0x1 Stop Sleep Negotiation on link-down:

1b = Stop Sleep Negotiation when link is down in Sleep Ack or Sleep Request states
LPS_CFG3 0x018C 7:0 cfg_lps_pwr_mode RH/W1S 0x0 One hot enable for each LPS state:

Bit 0: Set to 1 for Normal Mode

Bit 1: Set to 1 for enabling local_sleep_req

Bit 4: Set to 1 for Standby Mode

Bit 7: Set to 1 to enable WUR
A2D_REG_68 0x0444 0 wake_fwd_force_control R/W 0x0 WAKE Output Value Force Control:

1b = Force Control Enable. Output value is set by 0x0444[1]
1 wake_fwd_force_val R/W 0x0 WAKE Output Force Value:

0b = Force low on WAKE pin if 0x0444[0] = 1

1b = Force high on WAKE pin if 0x0444[0] = 1
2 goto_sleep_force_control R/W 0x0 Sleep Mode Force Control:

Set to 1 along with 0x0444[3] to force sleep mode
3 goto_sleep_force_val R/W 0x0 Sleep Mode Force Value:

Set to 1 along with 0x0444[2] to force sleep mode