SNLA417 January   2023 DP83TC812R-Q1 , DP83TC812S-Q1

 

  1.   Abstract
  2. 1Introduction
    1. 1.1 Acronyms
  3. 2TC10 Test Setup
    1. 2.1 Overview
    2. 2.2 Wakeup to Linking Sequence
  4. 3Measurement Summary
    1. 3.1 Complete Timing Diagram
    2. 3.2 Measurement Summary
    3. 3.3 LP1 Wake to Linking Time
  5. 4Timing Measurements
    1. 4.1 LP1 WAKE to INH (T1)
    2. 4.2 LP1 INH to WUP (T2)
    3. 4.3 WUP to PHY INH (T3)
    4. 4.4 PHY INH/Buck EN to Buck nRESET (T4)
    5. 4.5 Buck nRESET/PMIC Enable to MCU nReset (T5)
    6. 4.6 MCU nReset to MDIO Communication (T6 and T7)
    7. 4.7 MDIO Master Configuration + Linking (T8 and T9)
  6. 5Measurement Evaluation
    1. 5.1 Recommendations for Optimizing Variable TC10 Times
      1. 5.1.1 Improving MCU Boot-up Time (T6)
      2. 5.1.2 Improving MDIO State Machine (T7)
      3. 5.1.3 Optimizing MDIO Timeline (T8)
        1. 5.1.3.1 Optimizing Master Configuration by Removing Polling
        2. 5.1.3.2 Optimizing Master Configuration by Improving MDC
      4. 5.1.4 PHY Configuration During Sleep
      5. 5.1.5 Other Configurable Values
    2. 5.2 Alternative TC10 Test
  7. 6Conclusion
  8. 7References

3.2 Measurement Summary

Table 3-1 details the measurements.

Table 3-1 Summary of Measurements
IntervalTime Marker

Description

Measurements
tlink – tLP1_WAKE

LP1 WAKE going high to linking

(System wake to link time)

33.32ms + T*
T1tLP1_INH – tLP1_WAKELP1 WAKE going high to LP1 INH going high

(LP1 wake-up sequence started)

20.6μs
T2tWUP – tLP1_INH

LP1 INH going high to WUP being transmitted

10.53ms
T3tINH – tWUP

WUP being transmitted to LP2 INH going high

(LP2 wake-up sequence started)

45.8μs
T4tnRESET – tINH

LP2 INH going high to buck nRESET going high

(Buck ready)

6.00ms
T5tMCU_nRESET – tnRESET

Buck nRESET going high to MCU nRESET going high

(PMIC ready)

2.184ms
T6* tMDIO – tMCU_nRESET

MCU nReset going high to MDIO communication starting

(MCU start-up)

*
T7* tms_cfg_start – tMDIOMDIO communication starting to master configuration start*
T8* tms_cfg_end – tms_cfg_startMaster configuration time3.914ms*
T9tlink – tms_cfg_endEnd of master configuration to linking14.541ms