4 Fixed Latency and Recovered Clock Modes

In addition to supporting IEEE 802.1AS HW timestamping, The DP83TG721 and DP83TC817/8 have additional features that account for indeterministic latencies that occur as a result of the PHY.

For ADAS sensor applications, both devices offer the option of using the recovered MDI clock as the Wall Clock source. Using the recovered clock, the system can eliminate the ppm drift and associated compensation enabling better synchronization performance. Recovered clock also does not require continuous adjustments, freeing up software traffic and overhead. As a result, maximum throughput can be used with minimal affect on sync accuracy.

Figure 4-1 shows examples of point-to-point PPS synchronization using the local clock and using the recovered clock source on the DP83TG721. From the scope shots, using the recovered clock results in a 4.5ns delay and 0ns of jitter while using the local clock results in 3ns delay and 27ns of jitter.

For TI’s 100Base-T1 IEEE 802.1AS, a fixed latency feature has also been added to account for the latency variations that occur in the PCS layer of the PHY. The lower speed PHY (100Base-T1) PHY have larger latency variation due to slower clock speeds. Detailed architecture level considerations are needed to offer precise synchronization. These architecture level considerations have been added to minimize the effect of latency variation.

Below are some example measurements that had been taken with and without fixed latency mode with the DP83TC817. The scope shot using fixed latency mode shows 21ns of jitter while the scope shot without fixed latency shows 50ns of jitter, demonstrating a much better sync accuracy in fixed latency mode. By combining fixed latency mode and recovered clock mode, an even better synchronization accuracy is achieved with of 0ns of jitter and only 6.3ns of delay.