SNLU317A september   2022  – may 2023 DP83867E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
    2. 1.2 Hardware Features
    3. 1.3 Software Features
    4. 1.4 Block Diagram
  5. 2Board Overview
    1. 2.1 Components
    2. 2.2 PCIe Header Signals
      1. 2.2.1 MISC0 Signal Header
      2. 2.2.2 MISC1 Signal Header
      3. 2.2.3 RGMII Signal Header
  6. 3Quick Start
  7. 4Schematic, Board Layout, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematic
    3. 4.3 Bill of Materials
  8. 5Revision History

2.1 Components

Figure 2-1 below gives a quick overview of the AIC board. The marked sections are described in the Table 2-1.

GUID-20230427-SS0I-WFNR-RFRN-H9KLCGTNWWMF-low.jpg Figure 2-1 Connectors, Jumpers and LEDs
Table 2-1 Component Table
Section Description
1 RJ45 with integrated magnetic G-Bit network connection Port 1 / TSN_0
2 RJ45 with integrated magnetic G-Bit network connection Port 2 / TSN_1
3 DP83867 PHY1 for Port 1
4 DP83867 PHY2 for Port 2
5 25 MHz clock generation for both PHYs
6 Signal connector MISC0 for validation
7 Signal connector MISC1 for validation
8 Signal connector RGMII interface (optional)
9 PCIe interface
10 Power indicator LEDs.
  • D10: 3.3V indicator
  • D11: VDDIO indicator PHY1
  • D12: VDDIO indicator PHY2
  • D9: 3.3V indicator for optional SFP+ module
11 VDDIO voltage selector jumper pin-header
  • J19: PHY 1
    • Pin 1-2: 3.3V
    • Pin 2-3: 1.8V (default)
12 VDDIO voltage selector jumper pin-header
  • J21: PHY 1
    • Pin 1-2: 3.3V
    • Pin 2-3: 1.8V (default)
13 Shield/Earth GND for testing.