SNOA954D November   2019  – June 2021 LDC0851 , LDC1001 , LDC1001-Q1 , LDC1041 , LDC1051 , LDC1101 , LDC1312 , LDC1312-Q1 , LDC1314 , LDC1314-Q1 , LDC1612 , LDC1612-Q1 , LDC1614 , LDC1614-Q1 , LDC2112 , LDC2114 , LDC3114 , LDC3114-Q1

 

  1.   Trademarks
  2. 1LDC Applications
    1. 1.1 Axial Sensing
      1. 1.1.1 Buttons and Keypads
    2. 1.2 Event Counting
    3. 1.3 Other Types of Sensing
  3. 2Inductive Sensing Theory of Operation
  4. 3LDC Device Feature Overview
    1. 3.1 Sample Rate
    2. 3.2 Sensor L Measurement and Reference Frequency
    3. 3.3 Sensor RP Measurement
    4. 3.4 Sensor RP (Current) Drive Capability
    5. 3.5 Switch Output Functionality
    6. 3.6 Sensor Frequency Range
    7. 3.7 Multi-Channel Sensing
    8. 3.8 Power Management
    9. 3.9 Internal Algorithms
  5. 4Device Families
    1. 4.1 Inductive Touch Devices
      1. 4.1.1 Inductive Touch LDC Recommended Applications
    2. 4.2 Multichannel LDC Devices
      1. 4.2.1 Multi-Channel LDC Recommended Applications
      2. 4.2.2 LDC1101
        1. 4.2.2.1 LDC1101 Recommended Applications
      3. 4.2.3 LDC0851
        1. 4.2.3.1 Recommended Applications
  6. 5Summary
  7. 6Revision History

4.2 Multichannel LDC Devices

The Multichannel LDC family consists of the LDC1312, LDC1314, LDC1612, and the LDC1614.

GUID-DBE18FE1-4792-433D-97DC-F1DA9CE71BCC-low.gif Figure 4-2 LDC1614 Block Diagram

The main features of this architecture include:

  1. Multiple sensors on a single device – multiplexed 2 or 4 channels conversion, with excellent channel-channel matching
  2. Supply voltage range of 2.7 V to 3.6 V
  3. Deterministic sample rate of 40 SPS to 4.1 kSPS for the LDC1612/4
  4. Deterministic sample rate of 40 SPS to 13.3 kSPS for the LDC1312/4
  5. The widest sensor frequency range of 1 kHz to 10 MHz
  6. The highest maximum reference frequency of 40 MHz
  7. Two low power inactive modes – Sleep (typical < 35 μA) and Shutdown (typical <200 nA) make this family suitable for battery powered applications

The LDC161x devices feature 28 bits of resolution, while the LDC131x has an effective 16 bits of resolution.

The main limitation of these devices comes from the I2C bus bandwidth – while a single channel conversion can be read at up to 4 kSPS, when multiple channels are used the maximum retrievable sample rate decreases proportionally. One nice feature about this family of devices is the common register settings and common footprint – the programming and settings are compatible across all the devices in this family. In addition, the LDC1312 and LDC1612 share a 12-pin WSON package, and the LDC1314 and LDC1614 share a 16-pin WQFN package.