SNVA991 October   2022 LM5123-Q1

 

  1.   How to Design a Boost Converter Using LM5123
  2.   Trademarks
  3. 1Design Example
  4. 2Calculations and Component Selection
    1. 2.1  Switching Frequency
    2. 2.2  Initial Inductor Calculation
    3. 2.3  Current Sense Resistor Selection
    4. 2.4  Inductor Selection
    5. 2.5  Output Capacitor Selection
    6. 2.6  Input Capacitor Selection
    7. 2.7  Feedback Resistor Selection
    8. 2.8  UVLO Resistor Selection
    9. 2.9  Soft-Start Capacitor Selection
    10. 2.10 Control Loop Compensation
      1. 2.10.1 Crossover Frequency (fcross) Selection
      2. 2.10.2 RCOMP Selection
      3. 2.10.3 CCOMP Selection
      4. 2.10.4 CHF Selection
    11. 2.11 MOSFET selection
  5. 3Implementation Results
  6. 4Small Signal Frequency Modeling
    1. 4.1 Boost Regulator Modulator Modeling
    2. 4.2 Compensation Modeling
    3. 4.3 Open Loop Modeling
  7. 5Resources

2.11 MOSFET selection

The selection of the power MOSFETs has a significant impact on the DC-DC controllers performance. A MOSFET with low on-state resistance, RDSon, reduces conduction losses, where as low parasitic capacitance and low gate charge parameters reduces the switching losses. Normally, the RDSon and gate charge are inversely proportional. For relatively higher switching frequencies, MOSFET switching losses dominate. For relatively lower switching frequencies conduction losses dominate.

The main parameters affecting MOSFET selection for the LM5123 are as follows:

  • RDS(on) at VGS of 5 V.
  • Drain to source voltage rating, BVDSS, depending on the load voltage range.
  • Gate charge parameters at VGS of 5 V
  • Body diode reverse recovery charge, QRR, of the high-side MOSFET.

The MOSFET related power losses are summarized in Table 2-2. The influence of inductor ripple is considered but second order affect such as switch node ringing and parasitic inductance are not modeled.

Table 2-2 Boost Regulator MOSFET Power Losses
Low-Side MOSFET High-side MOSFET
MOSFET conduction P C O N D l s = D ∙ I L O A D 2 1 - D 2 + Δ I L 2 12 ∙ R D S ( o n ) l s P C O N D h s = 1 - D ∙ I L O A D 2 1 - D 2 + Δ I L 2 12 ∙ R D S o n h s
MOSFET switching (2) P S W l s =   V L O A D ∙ f s w 2 I S U P P L Y + Δ I L 2 ∙ t r i s e + I S U P P L Y - Δ I L 2 ∙ t f a l l Negligible
Body diode conduction N/A P C O N D d h s = V L O A D ∙ f s w 2 I S U P P L Y + Δ I L 2 ∙ t d 1 + I S U P P L Y - Δ I L 2 ∙ t d 2
Body diode reverse recovery losses(1) N/A P R R h s = V L O A D ∙ f S W ∙ Q R R h s
Gate drive losses P G A T E l s = V C C ∙ f S W ∙ Q G l s P G A T E h s = V C C ∙ f S W ∙ Q G h s
(1) MOSFET body diode revere recover charge (QRR) depends on many parameters including forward current, current transition and speed
(2) tRISE and tFALL are the rise and fall time of the switch node. These values depend on many parameters such as total switch node capacitance. Layout of the switch node will impact these values.