SNVA991 October   2022 LM5123-Q1

 

  1.   How to Design a Boost Converter Using LM5123
  2.   Trademarks
  3. 1Design Example
  4. 2Calculations and Component Selection
    1. 2.1  Switching Frequency
    2. 2.2  Initial Inductor Calculation
    3. 2.3  Current Sense Resistor Selection
    4. 2.4  Inductor Selection
    5. 2.5  Output Capacitor Selection
    6. 2.6  Input Capacitor Selection
    7. 2.7  Feedback Resistor Selection
    8. 2.8  UVLO Resistor Selection
    9. 2.9  Soft-Start Capacitor Selection
    10. 2.10 Control Loop Compensation
      1. 2.10.1 Crossover Frequency (fcross) Selection
      2. 2.10.2 RCOMP Selection
      3. 2.10.3 CCOMP Selection
      4. 2.10.4 CHF Selection
    11. 2.11 MOSFET selection
  5. 3Implementation Results
  6. 4Small Signal Frequency Modeling
    1. 4.1 Boost Regulator Modulator Modeling
    2. 4.2 Compensation Modeling
    3. 4.3 Open Loop Modeling
  7. 5Resources

2.5 Output Capacitor Selection

The output capacitor is required to smooth the load voltage ripple, provides an energy source during load transients. The output capacitor bank and the control loop bandwidth impact the dynamic load transient response of the regulator. The output capacitor delivers energy to the load until the control loop can adjust to the new operating point. The control loop crossover frequency is estimated to approximately 1/8 the right-half plan zero of the boost plant transfer function using Equation 11.

Equation 11. fCROSSest=ωRHP2π∙8=VSUPPLY22π∙8∙POUTmax∙LM=8V22π∙8∙200W∙2.6µH=2.45kHz

The estimated control loop crossover frequency estimated to be 2.45 kHz. Note that the minimum right-half plane zero frequency occurs at the minimum input voltage and maximum output power.

With the target crossover frequency selected, the minimum output capacitance is calculated based on the transient response for a given loaded step using Equation 12. In a variable output voltage design the maximum load step occurs at the minimum target load voltage and the output capacitance is sized accordingly.

Equation 12. C O U T e s t ≥ Δ I L O A D 2 π ∙ Δ V L O A D ∙ f C R O S S e s t = 4.167 A 2 π ∙ 360 m V ∙ 2.45 k H z = 752 µ F

where

  • ΔILOAD is the given load step. For this example is from half load to full load.
  • ΔVLOAD is the load voltage undershoot caused by the load transient. For this example the value is 1.5% of the target load voltage.

The calculated output capacitance is 752 μF, and for this design is selected to be 900 μF.

The output capacitor must be rated to handle the RMS current during the off time of the low-side switch. The maximum output ripple current is estimated using Equation 13.

Equation 13. I C O U T r m s = 1 - D I L O A D 2 ∙ D 1 - D 2 + Δ I L 2 12 = 1 - 0.667 8.33 A 2 ∙ 0.667 1 - 0.667 2 + 4.66 A 2 12 = 11.82   A

where

  • ΔIL is the peak to peak ripple of the

The estimated RMS current of the output capacitor bank is 11.82 A. Note the highest output capacitor RMS current occurs at the worst case operating condition, minimum supply voltage, maximum load voltage and full power. The output capacitor bank is comprised of both electrolytic capacitors and ceramic capacitors. Each chemistry benefits the design. Electrolytic capacitors provide a large bulk capacitance for low frequency energy storage to handle load transient demands, in a relatively small footprint. Ceramic capacitors provide a low ESR and low ESL decoupling path to minimize switching noise being coupled to the load voltage. Ceramic capacitor typically has very high RMS current rating. Due to the benefits of each chemistry the output capacitor bank is comprised of both electrolytic and ceramic capacitors.