SNVU786 May   2021 LP5860

 

  1.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3. 1.1 Glossary
    4.     Related Documentation
    5. 1.1 Support Resources
    6.     Trademarks
  2. 1Introduction/Feature Overview
    1. 1.1 Overview
    2. 1.2 Description
  3. 2 Register Maps
    1. 2.1  Register Map Table
    2. 2.2  CONFIG Registers
    3. 2.3  GROUP Registers
    4. 2.4  LED_DOT_GROUP Registers
    5. 2.5  LED_DOT_ONOFF Registers
    6. 2.6  FAULT_STATE Registers
    7. 2.7  LOD Registers
    8. 2.8  LSD Registers
    9. 2.9  LOD_CLR Registers
    10. 2.10 LSD_CLR Registers
    11. 2.11 RESET Registers
    12. 2.12 DC Registers
    13. 2.13 PWM Registers
  4. 3Revision History

2.2 CONFIG Registers

Table 2-2 lists the CONFIG registers. All register offset addresses not listed in Table 2-2 should be considered as reserved locations and the register contents should not be modified.

Device Configuration

Table 2-2 CONFIG Registers
Address Acronym Register Name Section
0h Chip_en Chip enable Go
1h Dev_initial Device initialization Go
2h Dev_config1 Device configuration register 1 Go
3h Dev_config2 Device configuration register 2 Go
4h Dev_config3 Device configuration register 3 Go

2.2.1 Chip_en Register (Address = 0h) [Default = 0h]

Chip_en is shown in Figure 2-1 and described in Table 2-3.

Return to the Summary Table.

Figure 2-1 Chip_en Register
7 6 5 4 3 2 1 0
RESERVED Chip_EN
R-0h R/W-0h
Table 2-3 Chip_en Register Field Descriptions
Bit Field Type Default Description
7-1 RESERVED R 0h Reserved
0 Chip_EN R/W 0h Chip enable
0h = Disabled
1h = Enabled

2.2.2 Dev_initial Register (Address = 1h) [Default = 5Eh]

Dev_initial is shown in Figure 2-2 and described in Table 2-4.

Return to the Summary Table.

Figure 2-2 Dev_initial Register
7 6 5 4 3 2 1 0
RESERVED Max_Line_Num Data_Ref_Mode PWM_Fre
R-0h R/W-Bh R/W-3h R/W-0h
Table 2-4 Dev_initial Register Field Descriptions
Bit Field Type Default Description
7 RESERVED R 0h Reserved
6-3 Max_Line_Num R/W Bh Maximum scan line number selection
1h = 1 scan line (LED dot current must be set to lower than 20mA)
2h = 2 scan lines (LED dot current must be set to lower than 35mA)
3h = 3 scan lines
4h = 4 scan lines
5h = 5 scan lines
6h = 6 scan lines
7h = 7 scan lines
8h = 8 scan lines
9h = 9 scan lines
Ah = 10 scan lines
Bh = 11 scan lines
2-1 Data_Ref_Mode R/W 3h Data refresh mode slection
0h = Mode 1
1h = Mode 2
2h = Mode 3
3h = Mode 3
0 PWM_Fre R/W 0h Output PWM frequency setting
0h = 125kHz
1h = 62.5kHz

2.2.3 Dev_config1 Register (Address = 2h) [Default = 0h]

Dev_config1 is shown in Figure 2-3 and described in Table 2-5.

Return to the Summary Table.

Figure 2-3 Dev_config1 Register
7 6 5 4 3 2 1 0
RESERVED SW_BLK PWM_Scale_Mode PWM_Phase_Shift CS_ON_Shift
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 2-5 Dev_config1 Register Field Descriptions
Bit Field Type Default Description
7-4 RESERVED R 0h Reserved
3 SW_BLK R/W 0h Line switch blanking time setting
0h = 1us
1h = 0.5us
2 PWM_Scale_Mode R/W 0h Dimming scale setting of final PWM generator
0h = Linear scale dimming curve
1h = Exponential scale dimming curve
1 PWM_Phase_Shift R/W 0h PWM phase shift selection
0h = Phase shift off
1h = Phase shift on
0 CS_ON_Shift R/W 0h Current sink turn on delay setting
0h = Delay off
1h = Delay on

2.2.4 Dev_config2 Register (Address = 3h) [Default = 0h]

Dev_config2 is shown in Figure 2-4 and described in Table 2-6.

Return to the Summary Table.

Figure 2-4 Dev_config2 Register
7 6 5 4 3 2 1 0
Comp_Group3 Comp_Group2 Comp_Group1 LOD_removal LSD_removal
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 2-6 Dev_config2 Register Field Descriptions
Bit Field Type Default Description
7-6 Comp_Group3 R/W 0h Low brightness compensation clock shift number setting for group1
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
5-4 Comp_Group2 R/W 0h Low brightness compensation clock shift number setting for group2
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
3-2 Comp_Group1 R/W 0h Low brightness compensation clock shift number setting for group3
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
1 LOD_removal R/W 0h LOD removal function enable
0h = Disabled
1h = Enabled
0 LSD_removal R/W 0h LSD removal function enable
0h = Disabled
1h = Enabled

2.2.5 Dev_config3 Register (Address = 4h) [Default = 57h]

Dev_config3 is shown in Figure 2-5 and described in Table 2-7.

Return to the Summary Table.

Figure 2-5 Dev_config3 Register
7 6 5 4 3 2 1 0
Down_Deghost Up_Deghost Maximum_Current Up_Deghost_Enable
R/W-1h R/W-1h R/W-3h R/W-1h
Table 2-7 Dev_config3 Register Field Descriptions
Bit Field Type Default Description
7-6 Down_Deghost R/W 1h Downside deghosting level selection
0h = No deghosting
1h = Weak deghosting
2h = Medium deghosting
3h = Strong deghosting
5-4 Up_Deghost R/W 1h Scan line clamp voltage of upside deghosting
0h = VLED – 2V
1h = VLED – 2.5V
2h = VLED – 3V
3h = GND
3-1 Maximum_Current R/W 3h Maximum current cetting (MC)
0h = 3mA
1h = 5mA
2h = 10mA
3h = 15mA (Default)
4h = 20mA
5h = 30mA
6h = 40mA
7h = 50mA
0 Up_Deghost_Enable R/W 1h Current sink turn on delay enable
0h = Disabled
1h = Enabled