SNVU903A May   2024  – June 2025 LP87563-Q1

 

  1.   1
  2.   , , Technical Reference Manual
  3.   Trademarks
  4. 1Introduction
  5. 2Register Bits Loaded From OTP Memory
  6. 3Revision History

1 Introduction

This technical reference manual can be used as a reference for the LP875630C-Q1 default register bits after OTP memory download. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8756x-Q1 Four-Phase 16-A Buck Converter With Integrated Switches data sheet.

Table 1-1 lists the main OTP settings for power rails. Table 2-1 lists the register bits loaded from OTP memory.

Table 1-1 Main OTP Settings for Power Rails
DescriptionBit NameLP875630C-Q1 Value
Device identificationOTP configurationOTP_ID0x113
BUCK0, BUCK1 (2-phase operation)Output voltageBUCK0_VSET850 mV
Enable, EN pin, or I2C registerEN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECTEN1
Force PWMBUCK0_FPWMYes
Force multiphaseBUCK0_FPWM_MPYes
Peak current limit per phaseILIM0,ILIM15 A
Maximum load currentN/A8 A
Slew rateSLEW_RATE03.8 mV/µs
BUCK2Output voltageBUCK2_VSET3300 mV
Enable, EN pin, or I2C registerEN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECTEN1
Force PWMBUCK2_FPWMYes
Peak current limitILIM24 A
Maximum load currentN/A4 A
Slew rateSLEW_RATE23.8 mV/µs
BUCK3Output voltageBUCK3_VSET1800 mV
Enable, EN pin, or I2C registerEN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECTEN1
Force PWMBUCK3_FPWMYes
Peak current limitILIM34 A
Maximum load currentN/A4 A
Slew rateSLEW_RATE33.8 mV/µs
Switching frequencyN/A2 MHz
I2C addressN/A0x61
Note:

The maximum total output capacitance (local + POL) per phase (BUCK0, BUCK1, BUCK2, and BUCK3) depends on the slew rate setting. Check the data sheet for the allowed capacitance value.