SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

3.1 Crystal and Oscillator Input Options

The AM26x XTAL_XI and XTAL_XO clock input can be sourced from either an attached crystal or a single-ended oscillator output.

Crystal Clocking Mode

The attached crystal needs to be a fundamental mode crystal operating at 25MHz. The crystal requires shunt capacitors, with capacitance ranging from 12pF-24pF. Figure 3-1 shows an example of the AM26x being clocked in crystal mode.

Excerpt From AM263x Control Card Schematics (for full crystal and oscillator input requirements) Figure 3-1 Excerpt From AM263x Control Card Schematics (for full crystal and oscillator input requirements)

Oscillator Clocking Mode

If operating from a single-ended oscillator output, then the XTAL_XI pin needs to be connected to the oscillator and the XTAL_XO pin must be left floating, unconnected on the PCB. In oscillator input mode, the XTAL_XI pin can be tied to either a 1.8V square wave or sine wave oscillator. For full oscillator input requirements, see the device specific AM26x data sheet. Figure 3-2 shows an example of an AM26x clock tree using a clock distributor and buffer circuit.

Excerpt From AM263x controlCard Schematics - Oscillator Clock Source and Clock Distributor Figure 3-2 Excerpt From AM263x controlCard Schematics - Oscillator Clock Source and Clock Distributor

In the case of the AM263x Control Card, an onboard ABM10W-25.0000MHZ-8-K1Z-T3 25MHz crystal provides crystal mode clocking. Alternatively, an LMK1C1104PWR clock distributor circuit and SN74LV1T34 buffer provide the 1.8V square-wave clock to the XTAL_XI pin. The LMK1C1104PWR is also used to provide a clock source to the onboard Ethernet PHY.