SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

14.4.1 1.8V Key Layout Considerations - ZCZ

For ZCZ package devices, the AM263x controlCard EVM is explored as an example. Additional filtering for the local AM263x 1.8V PLL power net is done through the LC filter of ferrite-bead FL12 and associated capacitors. This is used to create an additional low-IR drop low-pass filter that attenuates any high frequency noise present on the 1.8V LDO analog output.

  • Wide, minimum 15 mil traces, needs to be used for all power and ground return via fan-out.
  • 1.8V digital and analog is generated from on-chip LDO and so is highly localized to the BGA pinout.
  • A tightly coupled, adjacent ground return reference plane needs to be used for best transient performance and EMI coupling.
  • Smaller power planes or wider traces needs to be used for minimal IR drop and best transient routing across the associated BGA pins.
  • Smaller packaged, higher-frequency decoupling capacitance needs to be placed directly on BGA fan-out vias with as small of a dog-bone to power and ground return vias as possible.
AM263x controlCARD Excerpt – 1.8V Digital Power Via Fan-Out and Plane Routing Layer 6 Figure 14-22 AM263x controlCARD Excerpt – 1.8V Digital Power Via Fan-Out and Plane Routing Layer 6
AM263x controlCARD Excerpt – 1.8V Digital Power Decoupling on Layer 10 Figure 14-23 AM263x controlCARD Excerpt – 1.8V Digital Power Decoupling on Layer 10
AM263x controlCARD Excerpt – 1.8V Analog Power Via Fan-Out and Plane Routing Layer 6 Figure 14-24 AM263x controlCARD Excerpt – 1.8V Analog Power Via Fan-Out and Plane Routing Layer 6
Note: Figure 2-14 shows an example of an unacceptable routing between the FL12 filter output and the BGA pads. The output of the FL12 filter needs to be routed as a wide trace or small plane, and not smaller traces as was done on this initial revision of the controlCard EVM.
AM263x controlCARD Excerpt – 1.8V Analog Power Decoupling on Layer 10 Figure 14-25 AM263x controlCARD Excerpt – 1.8V Analog Power Decoupling on Layer 10