SPRACN9E september 2022 – may 2023 AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
Once the simulation successfully completes, generate the DDR analysis reports from the simulation tool. There are several different parameters to be verified, detailed in this section. Each parameter is pass/fail, meaning each must meet the specified target to ensure the design has sufficient margin to operate at the target data rates.
Use the appropriate JEDEC Vref parameters (Vref_min, Vref_max, Vref_step, and Vref_set_tol) and mask parameters (share, height, width).