SPRACN9E september   2022  – may 2023 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4VEN-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Jacinto 7 LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

3.6.4 Simulation Results

The simulation results are provided for the LPDDR4 interface from a 10 layer design. These simulation targets must be met to ensure the design will operate at the desired level of performance.

CA simulations need to be verified at the DRAM pin/BGA. This includes:

  • Minimum ring-back margins at high/low levels (JEDEC)
  • Vix_CK ratio (JEDEC)
  • Jitter/noise margins with respect to the eye mask (JEDEC)
  • Peak-peak power noise
GUID-8E95677C-C4AF-404F-AD97-978935B297A5-low.gif Figure 3-11 LPDDR4 Simulation Results for CA

Data write simulations need to be verified at both the DRAM BGA pin and the DRAM pad. This includes:

  • Minimum ring-back margins at high/low levels (JEDEC)
  • Vix_CK ration (JEDEC)
  • Jitter/noise margins with respect to the eye mask (JEDEC)
  • Peak-peak power noise
GUID-67253AC0-178C-49F7-A2AA-0343681DAFB3-low.png Figure 3-12 LPDDR4 Simulation Results for Write

Data read simulations need to be verified at SOC. This includes:

  • Minimum ring-back margins at high/low levels
  • Jitter/noise margins with respect to the eye mask
  • Peak-peak power noise
GUID-93B19ECF-73CE-4A1C-8435-ECA411789BBC-low.png Figure 3-13 LPDDR4 Simulation Results for Read

The simulations results for read includes two sets for data, black and green. The black shows the design failed, as several bytes failed to meet the eye margins. The green is the simulation results of the same design, but with back-drilling the via stubs applied.