SPRACN9E september 2022 – may 2023 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4VEN-Q1 , TDA4VM , TDA4VM-Q1
Figure 2-4 shows an example placement for the DRA829 processor and the LPDDR4 memory device. The recommended spacing parameters for all Jacinto7 devices and the LPDDR4 devices are defined in Table 2-3. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.
Number | Parameter | MIN | MAX | UNIT |
---|---|---|---|---|
1 | X | 1200 | Mils | |
2 | Y | 250 | Mils |