SPRACP7 October   2019 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   AM65xx Time Synchronization Architecture
    1.     Trademarks
    2. 1 Introduction
    3. 2 AM65xx Time Sync Architecture
      1. 2.1 Functional Overview
      2. 2.2 Time Sync Components
        1. 2.2.1 TSR and CER
        2. 2.2.2 NAV_CPTS
        3. 2.2.3 DM_Timers and Timer Managers
        4. 2.2.4 PCIe With PTM
        5. 2.2.5 IEP Timers in ICSSGx
        6. 2.2.6 CPSW
        7. 2.2.7 GTC
    4. 3 Time-Synchronization Examples
      1. 3.1 AM65xx as the Time Master Server
      2. 3.2 Multi-Domain Time Synchronization Across PCIe Interconnect
      3. 3.3 Hand-Over and Recovery
    5. 4 Summary
    6. 5 References

3.3 Hand-Over and Recovery

In real systems, it is important to have secondary time masters or hold-over mechanisms when the primary time master is not available, or when the communication channel is broken. Since AM64xx time-sync architecture allows delta adjustment to a local clock source, it is natural to maintain the same adjustment values during the period when no new adjustment values are available.

In case of loss of primary time master, the AM65xx device can be designated as the backup time master, where it can seamlessly resume the role of distributing master time bases. When the primary time master resumes, the secondary time master can hand-off the mastership to the primary. Detailed handoff mechanisms should be designed to ensure that certain time bases do not roll back.