SPRACU1A October   2020  – June 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Trademarks
  2. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  3. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  VPP
    8. 2.8  Net Classes
    9. 2.9  DDR4 Signal Termination
    10. 2.10 VREF Routing
    11. 2.11 VTT
    12. 2.12 POD Interconnect
    13. 2.13 CK and ADDR_CTRL Topologies and Routing Guidance
    14. 2.14 Data Group Topologies and Routing Guidance
    15. 2.15 CK and ADDR_CTRL Routing Specification
      1. 2.15.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.15.2 CK and ADDR_CTRL Routing Limits
    16. 2.16 Data Group Routing Specification
      1. 2.16.1 DQLM - DQ Longest Manhattan Distance
      2. 2.16.2 Data Group Routing Limits
    17. 2.17 Bit Swapping
      1. 2.17.1 Data Bit Swapping
      2. 2.17.2 Address and Control Bit Swapping
  4. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  Net Classes
    8. 3.8  LPDDR4 Signal Termination
    9. 3.9  LPDDR4 VREF Routing
    10. 3.10 LPDDR4 VTT
    11. 3.11 CK and ADDR_CTRL Topologies
    12. 3.12 Data Group Topologies
    13. 3.13 CK and ADDR_CTRL Routing Specification
    14. 3.14 Data Group Routing Specification
    15. 3.15 Channel, Byte, and Bit Swapping
  5. 4Revision History

2.16.2 Data Group Routing Limits

Table 2-7 contains the routing specifications for DQS, DQ, and DM routing groups. Each byte lane is routed and matched independently.

To use length matching (in mils) instead of time delay (in ps), multiply the time delay (in ps) limit by 5. The microstrip routes propagate faster than stripline routes. A standard practice when using length matching is to divide the microstrip length by 1.1, to achieve a compensated length to normalize the microstrip length with the stripline length and to align with the delay limits provided (see Section 1.5).

Table 2-7 Data Group Routing Specifications
NumberParameterMINMAXUNIT
DRS31BYTE0 length500ps (10)
DRS32BYTE1 length500ps
DRS36DQSn+ to DQSn- skew0.4ps
DRS37DQSn to DQn skew (2)(3)2ps
DRS38Vias per trace2 (1)vias
DRS39Via count difference0 (9)vias
DRS310Center-to-center BYTEn to other DDR4 trace spacing (5)4w (4)
DRS311Center-to-center DQn to other DQn trace spacing (6)3w (4)
DRS312DQSn center-to-center spacing (7)(8)See notes below
DRS313DQSn center-to-center spacing to other net4w (4)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(3) Each DQS pair is length matched to its associated byte.
(4) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints).
(5) Other DDR4 trace spacing means other DDR4 net classes not within the byte.
(6) This applies to spacing within the net classes of a byte.
(7) DQS pair spacing is set to ensure proper differential impedance.
(8) The user must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer.
(9) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure DQn skew and DQSn to DQn skew maximums are not exceeded.
(10) PCB track length shown as ps is a normalized representation of length. 1 ps can be equated to 5 mils as a simple transformation. This is stripline equivalent length where velocity compensation must be used for all segments routed as microstrip track.