Figure 4-2 shows the setup for a simulation of the first few periods of settling for the example system rearranged as described in Dedicated ADC Concept. A 100ns S+H window will be used, which is much shorter than the time previously determined to be necessary for good settling under normal conditions (11.8 µs). Note that the portion of the input model which discharges the S+H capacitor between samples has been removed, so C_H will retain its charge between samples. Finally, note that the simulation is configured such that the initial voltage condition on C_H is 0 V while the voltage divider output is a voltage near full-scale (3.0 V). This will result in a simulation equivalent to a full-scale input setup.

Figure 4-2 Simulation Schematic for V2 on Dedicated ADC

Running a transient simulation for 30µs gives the results as shown in figure Figure 4-3. The settling error after the first sample is about 100 mV, which is then reduced to 5.4 mV and then 0.27 mV after the second and third samples, respectively. Since 1/2 LSB settling with a 3.0 V ADC range is about 0.37 mV, the system did eventually achieve good settling in response to a full-scale step response! However, this took three sample periods (30 µs) and assumed that the signal remained stationary after the step response.

Figure 4-3 Settling Simulation for V2 Circuit on Dedicated ADC

What is quite interesting about these results is that 11.8 µs of settling time was predicted as necessary for this circuit topology, but the ADC only had the S+H window open for three bursts of 100 ns, resulting in 300 ns of total sampling time. How then did the circuit achieve good settling?

For each sample, note that the error scales down by roughly a factor of 20. This corresponds to the ratio of the external ADC input capacitor, C_S (250 pF in this case), to the internal ADC S+H capacitor, C_H (12.5 pF in this case). When the S+H first opens, these two capacitors quickly equalize, charging C_H 95% of the way towards the input voltage present on C_S.