SPRAD59 October   2023 TMS320F280039

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Key Differences Between DCAN and MCAN
  6. 3 Module Initialization
    1. 3.1 DCAN Initialization
    2. 3.2 MCAN Initialization
    3. 3.3 Initialization sequence
    4. 3.4 Code Snippets for Module Initialization
  7. 4 Bit Timing Configuration
  8. 5 Message RAM Configuration
  9. 6 Interrupt handling
    1. 6.1 MCAN Interrupt Sources
    2. 6.2 DCAN Interrupt Handling
    3. 6.3 MCAN Interrupt Handling
  10. 7 Transmitting data
    1. 7.1 Basic Transmission Process
      1. 7.1.1 Transmission with DCAN
      2. 7.1.2 Transmission with MCAN
    2. 7.2 MCAN Vs DCAN Transmit Procedural Differences
    3. 7.3 MCAN Transmit Concepts
      1. 7.3.1 Tx Event FIFO
  11. 8 Receiving Data
    1. 8.1 Introduction to Reception
    2. 8.2 Basic Reception Process
      1. 8.2.1 DCAN Reception
      2. 8.2.2 MCAN Reception
    3. 8.3 Filter Elements
      1. 8.3.1 Filter Element Structure
    4. 8.4 Rx Buffer
      1. 8.4.1 Receiving in Rx Buffer
    5. 8.5 Rx FIFO
      1. 8.5.1 Receiving in Rx FIFO
    6. 8.6 Receiving High Priority Messages
  12. 9 Avoiding network errors
  13. 10References

6.2 DCAN Interrupt Handling

Device-level Interrupt Configurations:

  1. Initialize PIE and PIE Vector Table. Enable Global and Real-time Interrupts.
  2. Configure the interrupt handler in the PIE Vector Table. Enable interrupt in the interrupt controller.

Module-level Interrupt Configurations

  1. Enable Error and Status interrupts, using the CAN Control Register (CAN_CTL). Enable Message Object interrupts while setting up Message Objects individually.
  2. Select interrupt line where each message object interrupt is to be routed using the register (CAN_IP_MUX21), where each bit corresponds to a single message object.
  3. Interrupt Service Routine (ISR) : Read Interrupt Register (CAN_INT) to determine the source of the interrupt (status/error/particular message object). Clear the Interrupt by writing to CAN Error and Status Register (CAN_ES) or by clearing the IntPnd bit in the corresponding Message Object. Clear the Global Interrupt Flag for the corresponding Interrupt Line.
  4. Acknowledge the interrupt via PIEACK.
GUID-20231010-SS0I-LP5R-W2W1-XSJVVNHRZXFR-low.png Figure 6-1 DCAN Interrupt Initialization
GUID-20231010-SS0I-DZXV-XG42-F0ZNPBQXST6K-low.png Figure 6-2 DCAN Interrupt handling