SPRAD67A december 2022 – july 2023 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The processor includes seven dual-voltage IO domains (VDDSHVx [x = 0..5] and VDDSHV_MCU), where each domain provides power to a fixed set of IOs. Each IO domain can be configured for 3.3 V or 1.8 V, which determines a common operating voltage for the entire set of IOs powered by the respective IO domain. All signals connected to these domains must operate from the same power source that is being used to power the respective VDDSHVx supply rail. Most of the IO buffers are not fail-safe (refer device-specific data sheet for fail-safe IOs). The supply voltage for the VDDSHVx rails must be present before any voltage is applied to the associated IOs.
IO grouping information is summarized below:
VDDSHV0 – Voltage for the General IO group
VDDSHV1 – Voltage for the PRG0 IO group
VDDSHV2 – Voltage for the PRG1 IO group
VDDSHV3 – Voltage for the GPMC IO group
VDDSHV4 – Voltage for the Flash IO group
VDDSHV5 – Voltage for the MMC1 IO group
VDDSHV_MCU – Voltage for the MCU General IO group