SPRAD96B November   2023  – January 2024 AM62P , AM62P-Q1

 

  1.   1
  2.   Trademarks
  3. 1 Introduction
  4. 2 Via Channel Arrays
  5. 3 Width/Spacing Proposal for Escapes
  6. 4 Stackup
  7. 5 Via Sharing
  8. 6 Floorplan Component Placement
  9. 7 Critical Interfaces Impact Placement
  10. 8 Routing Priority
  11. 9 SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary
  16. 14Revision History

3 Width/Spacing Proposal for Escapes

The AM62Px Via channel array solution has been designed to support the following. The AM62Px package supports a similar feature set as several other competition solutions with approximately 15% smaller package area and ~10% wider line width. This solution reduces the PCB foot print and utilizes lower cost PCB rules, enabling compact and low-cost systems.

Table 3-1 Width/Spacing Proposal for Escapes
PCB Feature PCB Routing Requirements
Minimum via pad diameter 18 mils
Via hole size 8 mils
Minimum trace width/spacing required in the BGA break out 4mil / 4mil
Number of layers used for escape 5
BGA land pad size 0.3 mm
Package Size 17 mm x 17 mm, 0.65/0.8-mm pitch w/ VCA
PCB layers (signal routing, total) recommended 4, 10
Solder resist clearance 0.07 mm max