The AM261x has a hardware USB controller that supports USB 3.0 with a software configurable architecture, has an internal DMA controller, descriptor caching, multiple transfer queueing support, Power saving features, Dynamic FIFO memory allocation for endpoints, low MIPS requirement and Interrupt moderation (in host mode) as well. This feature packed IP is integrated on the AM261x to work with the ARM R5F core. Figure 2-1 shows how the controller is interfaced with the R5F and the USB 2.0 PHY along with the memories it uses.

The USB on AM261x supports a Dual-Role-Device which supports 15 IN, 15 OUT endpoints and a bi-directional EP0 endpoint. The USB Subsystem provides four programmable interrupts and a miscellaneous interrupt line for other events. The USB subsystem works very well with high-bandwidth applications and portable-electronic devices.

The USB low-level driver is only involved in setting up the transfer descriptors and data structures. The software creates the transfer request buffers (TRBs) and allocates event buffers and data buffers in system memory. The hardware handles the complete data packaging and routing to pipes. The internal DMA controller and BMU handle the core DMA operations and data buffering requirements. The TRBs only contain the buffer pointers to the actual data buffers, the length of the data and the TRB control block data. The below image shows how a software initiated and configured transfer occurs.

The USB on AM261x can be statically configured to be the Host or Device at power-on. The OTG switch cannot be made on the run-time and is not supported in the hardware. The embedded PHY does not support the OTG features of USB-OTG standard (ID pin detection and VBUS detection). The AM261x has a USB Micro-AB port for connection to the external world.