SPRADP6A February   2025  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Net Checks
    1. 2.1 Verify Proper AM26x Power Rail Voltage Levels
    2. 2.2 Verify Maximum Current Loading
    3. 2.3 AM26x Power Sequencing
    4. 2.4 AM26x Power Topology References
  6. 3Device Boot Status
    1. 3.1 AM26x SOP Pin Status
    2. 3.2 SOP Boot Mode Latch Timing
    3. 3.3 AM26x SOP Pin Isolation
  7. 4Verify UART Output
    1. 4.1 Configure AM26x for UART Boot
    2. 4.2 Configure Host PC for UART Boot Validation
  8. 5Verify JTAG Connection
    1. 5.1 Configure AM26x for JTAG
    2. 5.2 Configure Host PC for JTAG Debug
    3. 5.3 Test the JTAG Connection
    4. 5.4 Connect to the AM26x R5F Core
  9. 6Loading and Executing a Code Example
    1. 6.1 Importing, Building, and Loading the Project
  10. 7Summary
  11. 8References
  12. 9Revision History

2.3 AM26x Power Sequencing

Once the device power nets and current loading have been verified, the power sequencing of the AM26x must be checked using an oscilloscope or a similar electronic test instrument. TI recommends to connect test wires or probe hooks to test points or exposed copper on the PCB to have a secure connection between the oscilloscope and the PCB.

Some key points to consider when verifying the AM26x power sequencing are:

  • There is no sequencing requirement with respect to the primary core digital VDD 1.2V and I/O power 3.3V rails
  • A pair of on-die LDO are supplied through the VDDS33 power net. These on-die LDOs generate the required VDDS1V8 and VDDA1V8 1.8V digital and analog power
  • The minimum ramp time for the 3.3V rail, tRamp_3V3 must be respected
  • Additional PORz and SOP boot mode latch timing must be respected by the PCB design
Note: For Industrial-grade AM261x devices ('O' speed grade), the core voltages VDD and VDDAR are 1.25V

Figure 2-1 shows the AM26x power-on sequencing. Table 2-3 describes the timing shown in Figure 2-1.

AM26x Power-On Sequencing Figure 2-1 AM26x Power-On Sequencing
Table 2-3 AM26x Power-On Sequencing Timing
PARAMETER MIN MAX UNIT
tStartup Time for 1.2V and 3.3V DC-DC converters to start up after being enabled. This is an arbitrary amount of time; no constraint imposed by the device. – – ms
tPGood Time for Power Good signals to be generated from DC-DC converters after rails are stable. This is an arbitrary amount of time - no constraint imposed by the device. – – ms
tRamp_3V3 Ramp time of the VDDS3V3 and VDDA3V3 supplies. This is a requirement imposed by the device. 0.1 – ms
tSOP_Sampled Time from PORz de-assertion until the SOP[3:0] pins are sampled. This is a device internal pentameter. Sampling happens when the internally generated supplies are stable. For information only. Refer to TSU_SOP and TH_SOP parameters for application usage. 0 – ms
tSU_SOP Setup time for SOP relative to PORz assertion. 10 – μs
tH_SOP Hold time for SOP relative to WARMRSTn deassertion. 0 – μs
tWARMRSTn Time from PORz de-assertion until the device deasserts the WARMRESETn signal. 2.0 – ms

Follow the steps below on the PCB and AM26x to boot the device from power-on reset (PORz):

  1. PORz is held low by the external power supply monitor.
  2. VDD core digital 1.2V and VDDS3V3/VDDA3V3 3.3V supplies ramp to the nominal voltages.
    1. This requires a logical AND be applied to the power good signal generated from each supply.
  3. SOP[3:0] pins held in the boot latch state.
  4. After PCB supplied power nets are stable, the external supply monitor deasserts PORz.
  5. Device starts up 1.8V on-die LDO.
  6. After internal supply monitors show externally and internally generated supplies are stable, the SOP[3:0] pin states are latched.
  7. R5F cores are unhalted and SOP selected boot ROM execution begins.

Once the power-on sequencing has been verified, the probes need to remain connected to the PCB to verify the power-down sequencing. Like with the power-on process, the order of power-down on the 1.2V and 3.3V rails do not matter.

Power-Down Sequencing Figure 2-2 Power-Down Sequencing