SPRSP65H April   2021  – December 2025 AM2431 , AM2432 , AM2434

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM243x ALV Pin Diagram
      2. 5.1.2 AM243x ALX Pin Diagram
    2. 5.2 Pin Attributes
      1.      13
      2.      14
      3. 5.2.1 AM243x Package Comparison Table (ALV vs. ALX)
    3. 5.3 Signal Descriptions
      1.      17
      2. 5.3.1  AM243x_ALX Package - Unsupported Interfaces and Signals
      3. 5.3.2  ADC
        1.       MAIN Domain Instances
          1.        21
      4. 5.3.3  CPSW
        1.       MAIN Domain Instances
          1.        24
          2.        25
          3.        26
          4.        27
      5. 5.3.4  CPTS
        1.       MAIN Domain Instances
          1.        30
          2.        31
      6. 5.3.5  DDRSS
        1.       MAIN Domain Instances
          1.        34
      7. 5.3.6  ECAP
        1.       MAIN Domain Instances
          1.        37
          2.        38
          3.        39
      8. 5.3.7  Emulation and Debug
        1.       MAIN Domain Instances
          1.        42
        2.       MCU Domain Instances
          1.        44
      9. 5.3.8  EPWM
        1.       MAIN Domain Instances
          1.        47
          2.        48
          3.        49
          4.        50
          5.        51
          6.        52
          7.        53
          8.        54
          9.        55
          10.        56
      10. 5.3.9  EQEP
        1.       MAIN Domain Instances
          1.        59
          2.        60
          3.        61
      11. 5.3.10 FSI
        1.       MAIN Domain Instances
          1.        64
          2.        65
          3.        66
          4.        67
          5.        68
          6.        69
          7.        70
          8.        71
      12. 5.3.11 GPIO
        1.       MAIN Domain Instances
          1.        74
          2.        75
        2.       MCU Domain Instances
          1.        77
      13. 5.3.12 GPMC
        1.       MAIN Domain Instances
          1.        80
      14. 5.3.13 I2C
        1.       MAIN Domain Instances
          1.        83
          2.        84
          3.        85
          4.        86
        2.       MCU Domain Instances
          1.        88
          2.        89
      15. 5.3.14 MCAN
        1.       MAIN Domain Instances
          1.        92
          2.        93
      16. 5.3.15 SPI (MCSPI)
        1.       MAIN Domain Instances
          1.        96
          2.        97
          3.        98
          4.        99
          5.        100
        2.       MCU Domain Instances
          1.        102
          2.        103
      17. 5.3.16 MMC
        1.       MAIN Domain Instances
          1.        106
          2.        107
      18. 5.3.17 OSPI
        1.       MAIN Domain Instances
          1.        110
      19. 5.3.18 Power Supply
        1.       112
      20. 5.3.19 PRU_ICSSG
        1.       MAIN Domain Instances
          1.        115
          2.        116
      21. 5.3.20 Reserved and No Connect
        1.       118
      22. 5.3.21 SERDES
        1.       MAIN Domain Instances
          1.        121
      23. 5.3.22 System and Miscellaneous
        1. 5.3.22.1 Boot Mode Configuration
          1.        MAIN Domain Instances
            1.         125
        2. 5.3.22.2 Clocking
          1.        MCU Domain Instances
            1.         128
        3. 5.3.22.3 SYSTEM
          1.        MAIN Domain Instances
            1.         131
          2.        MCU Domain Instances
            1.         133
        4. 5.3.22.4 VMON
          1.        135
      24. 5.3.23 TIMER
        1.       MAIN Domain Instances
          1.        138
        2.       MCU Domain Instances
          1.        140
      25. 5.3.24 UART
        1.       MAIN Domain Instances
          1.        143
          2.        144
          3.        145
          4.        146
          5.        147
          6.        148
          7.        149
        2.       MCU Domain Instances
          1.        151
          2.        152
      26. 5.3.25 USB
        1.       MAIN Domain Instances
          1.        155
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  eMMCPHY Electrical Characteristics
      5. 6.7.5  SDIO Electrical Characteristics
      6. 6.7.6  LVCMOS Electrical Characteristics
      7. 6.7.7  ADC12B Electrical Characteristics (ALV package)
      8. 6.7.8  ADC10B Electrical Characteristics (ALX package)
      9. 6.7.9  USB2PHY Electrical Characteristics
      10. 6.7.10 SerDes PHY Electrical Characteristics
      11. 6.7.11 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing
          2. 6.11.2.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
        2. 6.11.3.2 Safety Signal Timing
        3. 6.11.3.3 Clock Timing
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 Load Capacitance
            2. 6.11.4.1.1.2 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 6.11.4.2 Output Clocks
        3. 6.11.4.3 PLLs
        4. 6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  CPSW3G
          1. 6.11.5.1.1 CPSW3G MDIO Timing
          2. 6.11.5.1.2 CPSW3G RMII Timing
          3. 6.11.5.1.3 CPSW3G RGMII Timing
          4. 6.11.5.1.4 CPSW3G IOSETs
        2. 6.11.5.2  DDRSS
        3. 6.11.5.3  ECAP
        4. 6.11.5.4  EPWM
        5. 6.11.5.5  EQEP
        6. 6.11.5.6  FSI
        7. 6.11.5.7  GPIO
        8. 6.11.5.8  GPMC
          1. 6.11.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.11.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.11.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 6.11.5.8.4 GPMC0 IOSETs (ALV)
        9. 6.11.5.9  I2C
        10. 6.11.5.10 MCAN
        11. 6.11.5.11 MCSPI
          1. 6.11.5.11.1 MCSPI — Controller Mode
          2. 6.11.5.11.2 MCSPI — Peripheral Mode
        12. 6.11.5.12 MMCSD
          1. 6.11.5.12.1 MMC0 - eMMC Interface
            1. 6.11.5.12.1.1 Legacy SDR Mode
            2. 6.11.5.12.1.2 High Speed SDR Mode
            3. 6.11.5.12.1.3 High Speed DDR Mode
            4. 6.11.5.12.1.4 HS200 Mode
          2. 6.11.5.12.2 MMC1 - SD/SDIO Interface
            1. 6.11.5.12.2.1 Default Speed Mode
            2. 6.11.5.12.2.2 High Speed Mode
            3. 6.11.5.12.2.3 UHS–I SDR12 Mode
            4. 6.11.5.12.2.4 UHS–I SDR25 Mode
            5. 6.11.5.12.2.5 UHS–I SDR50 Mode
            6. 6.11.5.12.2.6 UHS–I DDR50 Mode
            7. 6.11.5.12.2.7 UHS–I SDR104 Mode
        13. 6.11.5.13 CPTS
        14. 6.11.5.14 OSPI
          1. 6.11.5.14.1 OSPI0 PHY Mode
            1. 6.11.5.14.1.1 OSPI0 With PHY Data Training
            2. 6.11.5.14.1.2 OSPI0 Without Data Training
              1. 6.11.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 6.11.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 6.11.5.14.2 OSPI0 Tap Mode
            1. 6.11.5.14.2.1 OSPI0 Tap SDR Timing
            2. 6.11.5.14.2.2 OSPI0 Tap DDR Timing
        15. 6.11.5.15 PCIe
        16. 6.11.5.16 PRU_ICSSG
          1. 6.11.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 6.11.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 6.11.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 6.11.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 6.11.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 6.11.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 6.11.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.11.5.16.2.1 PRU_ICSSG PWM Timing
          3. 6.11.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.16.3.1 PRU_ICSSG IEP Timing
          4. 6.11.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.16.4.1 PRU_ICSSG UART Timing
          5. 6.11.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 6.11.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.11.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 6.11.5.16.6.2 PRU_ICSSG MII Timing
            3. 6.11.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 6.11.5.17 Timers
        18. 6.11.5.18 UART
        19. 6.11.5.19 USB
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 Trace
        2. 6.11.6.2 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 7.2.2 Arm Cortex-M4F (M4FSS)
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 7.4 Other Subsystems
      1. 7.4.1 PDMA Controller
      2. 7.4.2 Peripherals
        1. 7.4.2.1  ADC
        2. 7.4.2.2  DCC
        3. 7.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 7.4.2.4  ECAP
        5. 7.4.2.5  EPWM
        6. 7.4.2.6  ELM
        7. 7.4.2.7  ESM
        8. 7.4.2.8  GPIO
        9. 7.4.2.9  EQEP
        10. 7.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 7.4.2.11 I2C
        12. 7.4.2.12 MCAN
        13. 7.4.2.13 MCRC Controller
        14. 7.4.2.14 MCSPI
        15. 7.4.2.15 MMCSD
        16. 7.4.2.16 OSPI
        17. 7.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 7.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 7.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 7.4.2.20 Dual Mode Timer (DMTIMER)
        21. 7.4.2.21 UART
        22. 7.4.2.22 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 General Routing Guidelines
      2. 8.2.2 DDR Board Design and Layout Guidelines
      3. 8.2.3 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.3.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.3.2 External Board Loopback
        3. 8.2.3.3 DQS (only available in Octal SPI devices)
      4. 8.2.4 USB VBUS Design Guidelines
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 High Speed Differential Signal Routing Guidance
      7. 8.2.7 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
      2. 8.3.2 Oscillator Ground Connection
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
      1. 9.3.1 Information About Cautions and Warnings
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
6.11.2.2.2 Power-Down Sequencing

Table 6-6 and Figure 6-6 describe the device power-down sequencing.

Note: All power rails must be turned off and decay below 300mV before initiating a new power-up sequence anytime a power rail drops below the minimum value defined in Recommended Operating Conditions.
Table 6-6 Power-Down Sequencing – Supply / Signal Assignments See: Figure 6-6
WAVEFORM SUPPLY / SIGNAL NAME
A VSYS, VMON_VSYS
B VDDSHV_MCU(1), VDDSHV0(1), VDDSHV1(1), VDDSHV2(1), VDDSHV3(1), VDDSHV4(1),VDDA_3P3_USB0, VMON_3P3_SOC, VMON_3P3_MCU
C VDDSHV_MCU(2), VDDSHV0(2), VDDSHV1(2), VDDSHV2(2), VDDSHV3(2), VDDSHV4(2), VDDA_MCU, VDDS_OSC, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_SOC, VMON_1P8_MCU, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0
D VDDA_3P3_SDIO(3)(4), VDDSHV5(3)
E VDDS_DDR(5), VDDS_DDR_C(5)
G VDD_CORE(6), VDDA_0P85_USB0(6), VDDA_0P85_SERDES0(6), VDDA_0P85_SERDES0_C(6), VDD_MMC0(6), VDDA_DLL_MMC0(6), VDDR_CORE(6)
H VPP
I MCU_PORz
J MCU_OSC0_XI, MCU_OSC0_XO
(1) VDDSHV_MCU and VDDSHVx [x=0-4] when operating at 3.3V.
(2) VDDSHV_MCU and VDDSHVx [x=0-4] when operating at 1.8V.
(3) VDDA_3P3_SDIO was designed to support power-up or power-down without any dependency on other power rails. VDDSHV5 is a dual voltage IO supply that was designed to support power-up, power-down, or dynamic voltage change without any dependency on other power rails. This capability is required to support UHS-I SD Cards.
(4) VDDA_3P3_SDIO is the 3.3V power rail for the internal SDIO_LDO. This power rail must be sourced from the same 3.3V power supply that provides power to a UHS-I SD Card connected to MMC1, which allows the MMC1 IOs and the SD Card IOs to power-up and power-down at the same time when the SD Card power supply is powered off to reset the SD Card. For this use case the SDIO_LDO output (CAP_VDDSHV_MMC1) is used to power the VDDSHV5 IO power rail, which will ramp-up and ramp-down along with the VDDA_3P3_SDIO power rail.
(5) VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together.
(6) VDD_CORE, VDDA_0P85_USB0, VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, VDD_MMC0, VDDA_DLL_MMC0, and VDDR_CORE are expected to be powered by the same 0.85V source such that they ramp together.
AM2434 AM2432 AM2431 Power-Down Sequencing Figure 6-6 Power-Down Sequencing