SPRUIF3B May   2017  – March 2019 DRA790 , DRA791 , DRA793 , DRA797

 

  1.   DRA79x EVM CPU board
    1.     Trademarks
    2. 1 Introduction
    3. 2 Overview
      1. 2.1 EVM System Configurations
      2. 2.2 CPU Board Feature List
      3. 2.3 CPU Board Component Identification
    4. 3 Hardware
      1. 3.1 Hardware Architecture
      2. 3.2 DRA71x, DRA79x, TDA2E-17, and AM570x Processor
      3. 3.3 Power Architecture
      4. 3.4 Reset Structure
      5. 3.5 Clocks
      6. 3.6 Memory
        1. 3.6.1  SDRAM Memory
        2. 3.6.2  QSPI Flash Memory
        3. 3.6.3  EMMC Flash Memory
        4. 3.6.4  MicroSD Card Cage
        5. 3.6.5  GPMC NOR Flash Memory
        6. 3.6.6  GPMC NAND Flash Memory
        7. 3.6.7  Boot Modes
        8. 3.6.8  JTAG/Emulator and Trace
        9. 3.6.9  UART Terminal
        10. 3.6.10 DCAN and CAN Interfaces
        11. 3.6.11 Universal Serial Bus (USB)
        12. 3.6.12 Wired Ethernet
        13. 3.6.13 Video Output
          1. 3.6.13.1 HDMI Display
          2. 3.6.13.2 LCD Touch Panel
          3. 3.6.13.3 FPD-Link III Output/Panel
        14. 3.6.14 Video Input
          1. 3.6.14.1 Parallel Imaging
          2. 3.6.14.2 Serial Imaging
        15. 3.6.15 Mini-PCIe
        16. 3.6.16 Media Local Bus (MLB)
        17. 3.6.17 Audio
        18. 3.6.18 COM8 Module Interface
        19. 3.6.19 eFuse Programming Supply
        20. 3.6.20 User Interface LEDs
        21. 3.6.21 Power Monitoring
        22. 3.6.22 I2C Peripheral Map
        23. 3.6.23 GPIO List
        24. 3.6.24 I/O Expander List
        25. 3.6.25 Configuration EEPROM
    5. 4 Signal Multiplex Logic
      1. 4.1 GPMC and QSPI Selection (MUX A)
      2. 4.2 GPMC, VIN1, and VOUT3 Selection (MUX B)
      3. 4.3 GPMC and EMMC Selection (MUX C)
      4. 4.4 VIN2A and EMU Selection (MUX D, MUX E)
      5. 4.5 VIN2A and RGMII1 Selection (MUX F)
      6. 4.6 RGMII0 and VIN1B Selection (MUX J)
      7. 4.7 SPI2 and UART3 Selection (MUX K)
      8. 4.8 DCAN2 and I2C3 Selection (MUX L)
    6. 5 USB3 Supported Configurations
      1. 5.1 Option 1
      2. 5.2 Option 2
      3. 5.3 Option 3
    7. 6 References
  2.   Revision History

4.2 GPMC, VIN1, and VOUT3 Selection (MUX B)

Figure 10 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not shown in the table. The functions shown are intended to reflect those supported on the EVM. These functions include:

  • Memory Bus (GPMC): AD[15:0], A[12:0]
  • Video Input Port (VIN1A): CLK, HSYNC, VSYNC, DE, and D[23:0]
  • Video Output Port (VOUT3): CLK, HSYNC, VSYNC, DE, and D[23:0]
  • Boot Mode Selection (SYSBOOT): SYSBOOT[15:0]
spruif1_soc_pinmux_for_gpmc_vin1_vo.gifFigure 10. SoC Pinmux for GPMC, VIN1, and VOUT3

MUX B: Selects between NOR and NAND memories, LCD panel for video, and expansion. The selection is made using the I/O expander 2, bits P7 and P0. The defaults is set to enable GPMC to NOR and NAND memories – which is required for SYSBOOT mode latching. Figure 11 shows the MUX diagram for GPMC, VIN1, and VOUT3

spruif1_mux_diagram_for_gpmc_vin1_v.gifFigure 11. MUX Diagram for GPMC, VIN1, and VOUT3