SPRUIG3C January   2018  – August 2019 TDA4VM , TDA4VM-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Related Documentation
    3.     Trademarks
  2. 1Overview and Scope
    1. 1.1 Comparing VCOP and C7000
    2. 1.2 About this Document
      1. 1.2.1 Documentation Conventions
    3. 1.3 Output Format
    4. 1.4 Data Types
      1. 1.4.1 40-bit Incompatibilities
      2. 1.4.2 40-Bit Detection in Host Emulation Mode
    5. 1.5 SIMD Width
    6. 1.6 VCOP Virtual Machine
  3. 2Kernel API
    1. 2.1 Overview
    2. 2.2 Parameter Block
      1. 2.2.1 Tvals Structure
      2. 2.2.2 Pblock Manipulation
  4. 3Loop Control
    1. 3.1 Overview
    2. 3.2 Loop Control and Nested Loops
    3. 3.3 Repeat Loops
    4. 3.4 Compound Conditions
    5. 3.5 Early Exit
  5. 4Addressing
    1. 4.1 Overview
    2. 4.2 Streaming Engines
    3. 4.3 Streaming Address Generators
    4. 4.4 Indexed Addressing
    5. 4.5 Circular Addressing
  6. 5Operations
    1. 5.1 Load Operations
    2. 5.2 Store Operations
      1. 5.2.1 Predicated Stores
      2. 5.2.2 Scatter and Transposing Stores
      3. 5.2.3 Optimization of OFFSET_NP1-Based Transpose
      4. 5.2.4 Rounding Stores
      5. 5.2.5 Saturating Stores
    3. 5.3 Arithmetic Operations
      1. 5.3.1 Vector Compares
      2. 5.3.2 Multiplication with Rounding, Truncation, or Left Shift
    4. 5.4 Lookup and Histogram Table Operations
      1. 5.4.1 Determination of Table Size
      2. 5.4.2 Table Configuration
      3. 5.4.3 Copy-in Operation
      4. 5.4.4 Copy-out Operation
      5. 5.4.5 Index Adjustment from Non-zero Agen
      6. 5.4.6 Lookup Operation
      7. 5.4.7 Histogram Update Operation
      8. 5.4.8 16-Way Lookup and Histogram
  7. 6Performance
    1. 6.1 Overview
    2. 6.2 Compiler Requirements
    3. 6.3 Automatic Performance Profiling
    4. 6.4 Performance Options
  8.   A Warnings and Notes
    1.     A.1 Compatibility Warnings
    2.     A.2 Efficiency Warnings

1.2.1 Documentation Conventions

The following terms are used throughout the document:

  • VCC refers generically to either the VCOP Kernel-C compiler (vcc-arp32), or the VCOP Kernel-C migration tool (vcc7x).
  • Migration tool refers to vcc7x, and sometimes implicitly includes the virtual machine.
  • Function names init(), kernel(), and vloops() refer to the functions generated by the VCC tool to implement the kernel API. The real names are prepended with the name of the kernel. For example, for a kernel named image_filter the term “vloops() function” in this document refers to the image_filter_vloops() function generated by VCC.
  • The term tvals structure refers to the VCC-generated structure that holds values computed in the init() function and used by the vloops() function, corresponding to VCOPs pblock. See Section 2.3.1. An expression of the form tvals->pN refers to an arbitrary field from the tvals structure.
  • Symbols in angle brackets are placeholders for one of several values of the indicated type; for example <op> represents some operation, <type> represents some type, and so on.

In code sequences in either the text or the tables, the following symbolic conventions are used:

  • A symbol starting with an upper-case V is either a VCOP or C7x vector register or a variable that represents such a register: Vsrc, Vdst, Vtmp, Vpred, etc.
  • An operand starting with Vperm is a C7x vector register containing a pre-computed vector for use with a VPERM instruction.
  • An operand starting with upper-case S is a C7x scalar variable or register: Sreg, Stmp, etc.
  • An operand starting with upper-case C is a C7x scalar constant: Cwidth, Csize, etc.
  • An operand starting with upper-case P is a C7x vector predicate: Pred, Pnz, etc. Pmask is a special vector predicate used to select certain lanes. Symbols of the form P8b, P8h, P8w and so on are precomputed vector predicates used as lane masks for partial vector stores; for example P8h is a mask for storing 8 halfwords. See Section 5.3.
  • Addr represents a C7x indirect address expression, perhaps with an register or SA-based offset or index, for example *A4, *A4[A0], or *B0[SA0++].
  • Symbols base, in, and out represent the base address in a VCOP load or store. A base address can be an expression, or a value loaded from the tvals structure (see Section 2.3).
  • A symbol that begins with Agen represents either a VCOP address generator declared with __agen, or the C7x variable or register that represents its translation.

    SEn refers to a C7x Streaming Engine access, either SE0 or SE1. Similarly SAn refers to a C7x Streaming Address Generator access.