SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

6.4.14.8 PRU_UART_UART0 Registers

Table 6-1039 lists the memory-mapped registers for the PRU_UART_UART0 registers. All register offset addresses not listed in Table 6-1039 should be considered as reserved locations and the register contents should not be modified.

Table 6-1038 PRU_UART_UART0 Instances

Instance	Base Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8000h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8000h

Table 6-1039 PRU_UART_UART0 Registers

Offset	Acronym	Register Name	PRU_ICSSG0_PR1_ICSS_UART_UART_SLV Physical Address	PRU_ICSSG1_PR1_ICSS_UART_UART_SLV Physical Address
0h	UART_RBR_TBR	Receive and Transmit Buffer Registers	3002 8000h	300A 8000h
4h	UART_INT_EN	UART Interrupt Enable Register	3002 8004h	300A 8004h
8h	UART_INT_FIFO	Interrupt Identification Register / FIFO Control Register	3002 8008h	300A 8008h
Ch	UART_LCTR	Line Control Register	3002 800Ch	300A 800Ch
10h	UART_MCTR	Modem Control Register	3002 8010h	300A 8010h
14h	UART_LSR1	Line Status Register1	3002 8014h	300A 8014h
18h	UART_MSR	Modem Status Register	3002 8018h	300A 8018h
1Ch	UART_SCRATCH	UART Scratch Register	3002 801Ch	300A 801Ch
20h	UART_DIVLSB	UART Divisor Register	3002 8020h	300A 8020h
24h	UART_DIVMSB	UART Divisor Register	3002 8024h	300A 8024h
28h	UART_PID	Peripheral ID Register	3002 8028h	300A 8028h
30h	UART_PWR	UART Power Management and Emulation Register	3002 8030h	300A 8030h
34h	UART_MODE	UART Mode Definition Register	3002 8034h	300A 8034h

4.14.8.1 UART_RBR_TBR Register (Offset = 0h) [reset = X]

UART_RBR_TBR is shown in Figure 6-529 and described in Table 6-1041.

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Table 6-1040 UART_RBR_TBR Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8000h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8000h

Figure 6-529 UART_RBR_TBR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														TBR_DATA										RBR_DATA
R/W-X														W-0h										R-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 6-1041 UART_RBR_TBR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R/W	X
17-8	TBR_DATA	W	0h	Transmit Buffer Register
7-0	RBR_DATA	R	0h	Receive Buffer Register

4.14.8.2 UART_INT_EN Register (Offset = 4h) [reset = X]

UART_INT_EN is shown in Figure 6-530 and described in Table 6-1043.

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UART Interrupt Enable Register

Table 6-1042 UART_INT_EN Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8004h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8004h

Figure 6-530 UART_INT_EN Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED				EDSSI	ELSI	ETBEI	ERBI
R/W-X				R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1043 UART_INT_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R/W	X
3	EDSSI	R/W	0h	Enable for Modem Status Interrupt
2	ELSI	R/W	0h	Enable for Receiver Line Status Interrupt
1	ETBEI	R/W	0h	Enable for Transmitter Holding Register Empty Interrupt
0	ERBI	R/W	0h	Enable for Receiver Data Available Interrupt

4.14.8.3 UART_INT_FIFO Register (Offset = 8h) [reset = X]

UART_INT_FIFO is shown in Figure 6-531 and described in Table 6-1045.

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Interrupt Identification Register / FIFO Control Register

Table 6-1044 UART_INT_FIFO Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8008h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8008h

Figure 6-531 UART_INT_FIFO Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
FCR_RXFIFTL		RESERVED		FCR_DMAMODE1	FCR_TXCLR	FCR_RXCLR	FCR_FIFOEN
W-0h		R/W-X		W-0h	W-0h	W-0h	W-0h

7	6	5	4	3	2	1	0
IIR_FIFOEN		RESERVED		IIR_INTID			IIR_IPEND
R-0h		R/W-X		R-0h			R-1h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 6-1045 UART_INT_FIFO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-14	FCR_RXFIFTL	W	0h	Receiver Trigger Level
13-12	RESERVED	R/W	X
11	FCR_DMAMODE1	W	0h	DMA Mode Select
10	FCR_TXCLR	W	0h	Transmitter FIFO Reset
9	FCR_RXCLR	W	0h	Receiver FIFO Reset
8	FCR_FIFOEN	W	0h	FIFO Enable Register
7-6	IIR_FIFOEN	R	0h	FIFOs enabled
5-4	RESERVED	R/W	X
3-1	IIR_INTID	R	0h	Interrupt Type
0	IIR_IPEND	R	1h	Receiver Data Available Interrupt Pending

4.14.8.4 UART_LCTR Register (Offset = Ch) [reset = X]

UART_LCTR is shown in Figure 6-532 and described in Table 6-1047.

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Line Control Register

Table 6-1046 UART_LCTR Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 800Ch
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 800Ch

Figure 6-532 UART_LCTR Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
DLAB	BC	SP	EPS	PEN	STB	WLS1	WLS0
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1047 UART_LCTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7	DLAB	R/W	0h	Divisor Latch Access Bit
6	BC	R/W	0h	Break Control
5	SP	R/W	0h	Stick Parity
4	EPS	R/W	0h	Even Parity Select
3	PEN	R/W	0h	Parity Enable
2	STB	R/W	0h	Number of Stop Bits
1	WLS1	R/W	0h	Word Length Select Bit 1
0	WLS0	R/W	0h	Word Length Select Bit 0

4.14.8.5 UART_MCTR Register (Offset = 10h) [reset = X]

UART_MCTR is shown in Figure 6-533 and described in Table 6-1049.

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Modem Control Register

Table 6-1048 UART_MCTR Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8010h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8010h

Figure 6-533 UART_MCTR Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED		AFE	LOOP	OUT2	OUT1	RTS	DTR
R/W-X		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1049 UART_MCTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R/W	X
5	AFE	R/W	0h	Autoflow Control Enable
4	LOOP	R/W	0h	LOOP Bit
3	OUT2	R/W	0h	Out2 Bit
2	OUT1	R/W	0h	Out1 Bit
1	RTS	R/W	0h	Ready to Send
0	DTR	R/W	0h	Data Terminal Ready

4.14.8.6 UART_LSR1 Register (Offset = 14h) [reset = X]

UART_LSR1 is shown in Figure 6-534 and described in Table 6-1051.

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Line Status Register1

Table 6-1050 UART_LSR1 Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8014h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8014h

Figure 6-534 UART_LSR1 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RXFIFOE	TEMT	THRE	BI	FE	PE	OE	DR
R-0h	R-1h	R-1h	R-0h	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1051 UART_LSR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	X
7	RXFIFOE	R	0h	Receiver FIFO Error
6	TEMT	R	1h	Transmitter Empty
5	THRE	R	1h	Transmitter Holding Register
4	BI	R	0h	Break Interrupt
3	FE	R	0h	Framing Error
2	PE	R	0h	Parity Error
1	OE	R	0h	Overrun Error
0	DR	R	0h	Data Ready

4.14.8.7 UART_MSR Register (Offset = 18h) [reset = X]

UART_MSR is shown in Figure 6-535 and described in Table 6-1053.

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Modem Status Register

Table 6-1052 UART_MSR Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8018h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8018h

Figure 6-535 UART_MSR Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
CD	RI	DSR	CTS	DCD	TERI	DDSR	DCTS
R-X	R-X	R-X	R-X	R-0h	R-0h	R-0h	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 6-1053 UART_MSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	X
7	CD	R	X	Carrier Detect
6	RI	R	X	Ring Indicator
5	DSR	R	X	Data Set Ready
4	CTS	R	X	Clear To Send
3	DCD	R	0h	Delta Carrier Detect
2	TERI	R	0h	Trailing Edge Ring Indicator
1	DDSR	R	0h	Delta Set Ready
0	DCTS	R	0h	Delta Clear To Send

4.14.8.8 UART_SCRATCH Register (Offset = 1Ch) [reset = X]

UART_SCRATCH is shown in Figure 6-536 and described in Table 6-1055.

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UART Scratch Register

Table 6-1054 UART_SCRATCH Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 801Ch
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 801Ch

Figure 6-536 UART_SCRATCH Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DATA
R/W-X																								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1055 UART_SCRATCH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-0	DATA	R/W	0h	Scratch Register Bits

4.14.8.9 UART_DIVLSB Register (Offset = 20h) [reset = X]

UART_DIVLSB is shown in Figure 6-537 and described in Table 6-1057.

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UART Divisor Register

Table 6-1056 UART_DIVLSB Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8020h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8020h

Figure 6-537 UART_DIVLSB Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DLL
R/W-X																								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1057 UART_DIVLSB Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-0	DLL	R/W	0h	Divisor Latch [LSB]

4.14.8.10 UART_DIVMSB Register (Offset = 24h) [reset = X]

UART_DIVMSB is shown in Figure 6-538 and described in Table 6-1059.

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UART Divisor Register

Table 6-1058 UART_DIVMSB Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8024h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8024h

Figure 6-538 UART_DIVMSB Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DLH
R/W-X																								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1059 UART_DIVMSB Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R/W	X
7-0	DLH	R/W	0h	Divisor Latch [MSB]

4.14.8.11 UART_PID Register (Offset = 28h) [reset = 44141102h]

UART_PID is shown in Figure 6-539 and described in Table 6-1061.

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Peripheral ID Register

Table 6-1060 UART_PID Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8028h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8028h

Figure 6-539 UART_PID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PID
R-44141102h

LEGEND: R = Read Only; -n = value after reset

Table 6-1061 UART_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PID	R	44141102h

4.14.8.12 UART_PWR Register (Offset = 30h) [reset = X]

UART_PWR is shown in Figure 6-540 and described in Table 6-1063.

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UART PowerManagement and Emulation Register

Table 6-1062 UART_PWR Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8030h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8030h

Figure 6-540 UART_PWR Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
URST	UTRST	URRST	RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-X

7	6	5	4	3	2	1	0
RESERVED						RES	FREE
R/W-X						R-1h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 6-1063 UART_PWR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15	URST	R/W	0h	UART Reset
14	UTRST	R/W	0h	UART Transmitter Reset
13	URRST	R/W	0h	UART Receiver Reset
12-2	RESERVED	R/W	X
1	RES	R	1h	Free
0	FREE	R/W	0h	Free

4.14.8.13 UART_MODE Register (Offset = 34h) [reset = X]

UART_MODE is shown in Figure 6-541 and described in Table 6-1065.

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UART Mode Definition Register

Table 6-1064 UART_MODE Instances

Instance	Physical Address
PRU_ICSSG0_PR1_ICSS_UART_UART_SLV	3002 8034h
PRU_ICSSG1_PR1_ICSS_UART_UART_SLV	300A 8034h

Figure 6-541 UART_MODE Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							OSM_SEL
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 6-1065 UART_MODE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	OSM_SEL	R/W	0h	Oversampling Mode Select