SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Interrupt Type | Description |
---|---|---|---|---|---|
DMSS0 |
VINTR_PEND[183:168] | NVIC_IN[47:32] | MCU_M4FSS0_CORE0 | Level | VINTR_PEND[183:168] interrupts to NVIC_IN |
VINTR_PEND[39:0] | SPI_IN[103:64] | GICSS0 |
Level |
VINTR_PEND[39:0] interrupts to GIC SPI | |
VINTR_PEND[71:40] | INTR_IN[95:64] | R5FSS0_CORE0 | Level | VINTR_PEND[79:40] interrupts to R5FSS0 CORE0 | |
VINTR_PEND[79:72] | INTR_IN[15:8] | ||||
VINTR_PEND[87:80] | INTR_IN[15:8] | R5FSS0_CORE1 | Level | VINTR_PEND[87:80][71:40] interrupts to R5FSS0 CORE1 | |
VINTR_PEND[71:40] | INTR_IN[95:64] | ||||
VINTR_PEND[127:120] | INTR_IN[16:8] | R5FSS1_CORE0 | Level | VINTR_PEND[127:88] interrupts to R5FSS1 CORE0 | |
VINTR_PEND[119:88] | INTR_IN[95:64] | ||||
VINTR_PEND[135:128] | INTR_IN[15:8] | R5FSS1_CORE1 | Level | VINTR_PEND[135:128][119:88] interrupts to R5FSS1 CORE1 | |
VINTR_PEND[119:88] | INTR_IN[95:64] | ||||
VINTR_PEND[151:136] | DMSC_lite[15:0] | DMSC_lite | Level | VINTR_PEND[151:136] interrupts to DMSC_lite | |
VINTR_PEND[159:152] | PR1_SLV_IN[7:0] | PRU_ICSSG0 | Level | VINTR[159:152] interrupts to PRU_ICSSG0 PR1 | |
VINTR_PEND[167:160] | PR1_SLV_IN[7:0] | PRU_ICSSG1 | Level | VINTR[167:160] interrupts to PRU_ICSSG1 PR1 | |
ECC_CORRECTED_ERR_LEVEL[0] | LVL_IN[9] | ESM0 | Level | SEC interrupt from ECC_AGGR0 | |
ECC_CORRECTED_ERR_PULSE[0] | LVL_IN[10] | Pulse | SEC interrupt from ECC_AGGR0 | ||
ECC_UNCORRECTED_ERR_LEVEL[0] | LVL_IN[72] | Level | DED interrupt from ECC_AGGR0 | ||
ECC_UNCORRECTED_ERR_PULSE[0] | LVL_IN[73] | Pulse | DED interrrupt from ECC_AGGR0 |