SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 5-406 lists the memory-mapped registers for the MAIN_SEC_MMR0_CFG2. All register offset addresses not listed in Table 5-406 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4590 0000h |
Offset | Acronym | Register Name | MAIN_SEC_MMR0_CFG2 Physical Address |
---|---|---|---|
0h | CTRLMMR_SEC_CLSTR0_CORE0_DBG_CFG | CLSTR0 Core0 Debug Configuration Register | 4590 0000h |
40h | CTRLMMR_SEC_CLSTR0_CORE1_DBG_CFG | CLSTR0 Core1 Debug Configuration Register | 4590 0040h |
1000h | CTRLMMR_SEC_CLSTR1_CORE0_DBG_CFG | CLSTR1 Core0 Debug Configuration Register | 4590 1000h |
1040h | CTRLMMR_SEC_CLSTR1_CORE1_DBG_CFG | CLSTR1 Core1 Debug Configuration Register | 4590 1040h |
9000h | CTRLMMR_SEC_CLSTR9_CORE0_DBG_CFG | CLSTR9 Core0 Debug Configuration Register | 4590 9000h |
9040h | CTRLMMR_SEC_CLSTR9_CORE1_DBG_CFG | CLSTR9 Core1 Debug Configuration Register | 4590 9040h |
10000h | CTRLMMR_SEC_CLSTR16_CORE0_DBG_CFG | CLSTR16 Core0 Debug Configuration Register | 4591 0000h |
10040h | CTRLMMR_SEC_CLSTR16_CORE1_DBG_CFG | CLSTR16 Core0 Debug Configuration Register | 4591 0040h |
CTRLMMR_SEC_CLSTR0_CORE0_DBG_CFG is shown in Figure 5-195 and described in Table 5-408.
Return to Summary Table.
Configures debug operation for R5FSS0 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4590 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBGEN | NIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | DBGEN | R/W | Ah | Core0 Invasive debug enable. |
11-8 | NIDEN | R/W | Ah | Core0 Non-invasive debug enable. |
7-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR0_CORE1_DBG_CFG is shown in Figure 5-196 and described in Table 5-410.
Return to Summary Table.
Configures debug operation for R5FSS0 Core1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4590 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBGEN | NIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | DBGEN | R/W | Ah | Core1 Invasive debug enable. |
11-8 | NIDEN | R/W | Ah | Core1 Non-invasive debug enable. |
7-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR1_CORE0_DBG_CFG is shown in Figure 5-197 and described in Table 5-412.
Return to Summary Table.
Configures debug operation for R5FSS1 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4590 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBGEN | NIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | DBGEN | R/W | Ah | Core0 Invasive debug enable. |
11-8 | NIDEN | R/W | Ah | Core0 Non-invasive debug enable. |
7-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR1_CORE1_DBG_CFG is shown in Figure 5-198 and described in Table 5-414.
Return to Summary Table.
Configures debug operation for R5FSS1 Core1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4590 1040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBGEN | NIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | DBGEN | R/W | Ah | Core1 Invasive debug enable. |
11-8 | NIDEN | R/W | Ah | Core1 Non-invasive debug enable. |
7-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR9_CORE0_DBG_CFG is shown in Figure 5-199 and described in Table 5-416.
Return to Summary Table.
Configures debug operation for A53SS9 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4590 9000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPNIDEN | SPIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NIDEN | DBGEN | ||||||
R/W-Ah | R/W-Ah | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | SPNIDEN | R/W | Ah | Core0 Secure Non-Invasive debug enable. |
11-8 | SPIDEN | R/W | Ah | Core0 Secure Invasive debug enable. |
7-4 | NIDEN | R/W | Ah | Core0 Non-Invasive debug enable. |
3-0 | DBGEN | R/W | Ah | Core0 Invasive debug enable. |
CTRLMMR_SEC_CLSTR9_CORE1_DBG_CFG is shown in Figure 5-200 and described in Table 5-418.
Return to Summary Table.
Configures debug operation for A53SS9 Core1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4590 9040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SPNIDEN | SPIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NIDEN | DBGEN | ||||||
R/W-Ah | R/W-Ah | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | SPNIDEN | R/W | Ah | Core1 Secure Non-Invasive debug enable. |
11-8 | SPIDEN | R/W | Ah | Core1 Secure Invasive debug enable. |
7-4 | NIDEN | R/W | Ah | Core1 Non-Invasive debug enable. |
3-0 | DBGEN | R/W | Ah | Core1 Invasive debug enable. |
CTRLMMR_SEC_CLSTR16_CORE0_DBG_CFG is shown in Figure 5-201 and described in Table 5-420.
Return to Summary Table.
Configures debug operation for M4FSS16 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4591 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DBGEN | NIDEN | ||||||
R/W-Ah | R/W-Ah | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | DBGEN | R/W | Ah | Core0 Invasive debug enable. |
11-8 | NIDEN | R/W | Ah | Core0 Non-invasive debug enable. |
7-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR16_CORE1_DBG_CFG is shown in Figure 5-202 and described in Table 5-422.
Return to Summary Table.
Reserved for M4FSS16.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG2 | 4591 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |