SPRUJ12F August   2021  – January 2024 AM2431 , AM2432 , AM2434

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 1.1 If You Need Assistance
    2. 1.2 Important Usage Notes
  5. 2Kit Overview
    1. 2.1 Kit Contents
    2. 2.2 Key Features
    3. 2.3 Component Identification
    4. 2.4 BoosterPacks
    5. 2.5 Compliance
    6. 2.6 Security
  6. 3Board Setup
    1. 3.1 Power Requirements
      1. 3.1.1 Power Input Using USB Type-C Connector
      2. 3.1.2 Power Status LED's
      3. 3.1.3 Power Tree
      4. 3.1.4 Power Sequence
    2. 3.2 Push Buttons
    3. 3.3 Boot Mode Selection
  7. 4Hardware Description
    1. 4.1  Functional Block Diagram
    2. 4.2  BoosterPack Headers
      1. 4.2.1 Pinmux for BoosterPack
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interface
      1. 4.6.1 QSPI Interface
      2. 4.6.2 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY Strapping
      2. 4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt
      3. 4.7.3 LED indication in Ethernet RJ45 Connector
    8. 4.8  USB 2.0 Interface
    9. 4.9  I2C Interface
    10. 4.10 Industrial Application LEDs
    11. 4.11 UART Interface
    12. 4.12 eQEP Interface
    13. 4.13 CAN Interface
    14. 4.14 FSI Interface
    15. 4.15 JTAG Emulation
    16. 4.16 Test Automation Interface
    17. 4.17 SPI Interface
  8. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  9.   A E3 Design Changes
  10.   B Revision A Design Changes
  11.   Revision History

4.12 eQEP Interface

The AM243x LaunchPad supports two eQEP interfaces. eQEP1 and eQEP2 of the AM243x SoC are connected to the eQEP headers. Both eQEP1 and eQEP2 headers need a voltage translation circuit (TXB0106RGYR) to level shift the IO's to 5 V from 3.3 V.

  • eQEP1_A, eQEP1_B, and eQEP1_I are directly connected to the eQEP header (J12) after voltage translation .
  • eQEP2_A, eQEP2_B are directly connected to the eQEP header (J21) after voltage translation. eQEP2_I requires an external 1:2 mux (TMUX154EDGSR) since eQEP2_I and MCAN0_TX come from the same pin (B13). Mux channel selection is done using SoC GPIO.

GUID-20210719-CA0I-66XC-PPBS-7RW0NQN05L59-low.png Figure 4-17 eQEP Interface
GUID-20210719-CA0I-DX6M-KHN7-VSWBGVQNXR4B-low.png Figure 4-18 eQEP1 Header
GUID-20210719-CA0I-G98D-HVTT-WKJ5LWRCXPLR-low.png Figure 4-19 eQEP2 Header
GUID-20210719-CA0I-8VL7-LXGT-KDHNRHVMZHJC-low.png Figure 4-20 eQEP2 or MCAN0 Mux Selection Circuit