SPRUJ40D May   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
  6. 2Hardware
    1. 2.1 System Description
      1. 2.1.1 Key Features
        1. 2.1.1.1 Thermal Compliance
        2. 2.1.1.2 Processor
        3. 2.1.1.3 Power Supply
        4. 2.1.1.4 Memory
        5. 2.1.1.5 JTAG/Emulator
        6. 2.1.1.6 Supported Interfaces and Peripherals
        7. 2.1.1.7 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
      2. 2.1.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
      3. 2.1.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
      4. 2.1.4 AM62x SKEVM Interface Mapping
      5. 2.1.5 Power ON/OFF Procedures
        1. 2.1.5.1 Power-On Procedure
        2. 2.1.5.2 Power-Off Procedure
        3. 2.1.5.3 Power Test Points
      6. 2.1.6 Peripheral and Major Component Description
        1. 2.1.6.1  Clocking
          1. 2.1.6.1.1 Peripheral Ref Clock
        2. 2.1.6.2  Reset
        3. 2.1.6.3  OLDI Display Interface
        4. 2.1.6.4  CSI Interface
        5. 2.1.6.5  Audio Codec Interface
        6. 2.1.6.6  HDMI Display Interface
        7. 2.1.6.7  JTAG Interface
        8. 2.1.6.8  Test Automation Header
        9. 2.1.6.9  UART Interface
        10. 2.1.6.10 USB Interface
          1. 2.1.6.10.1 USB 2.0 Type A Interface
          2. 2.1.6.10.2 USB 2.0 Type C Interface
        11. 2.1.6.11 Memory Interfaces
          1. 2.1.6.11.1 DDR4 Interface
          2. 2.1.6.11.2 OSPI Interface
          3. 2.1.6.11.3 MMC Interfaces
            1. 2.1.6.11.3.1 MMC0 - eMMC Interface
            2. 2.1.6.11.3.2 MMC1 - Micro SD Interface
            3. 2.1.6.11.3.3 MMC2 - Wilink Interface
          4. 2.1.6.11.4 EEPROM
        12. 2.1.6.12 Ethernet Interface
          1. 2.1.6.12.1 CPSW Ethernet PHY 2 Default Configuration
          2. 2.1.6.12.2 CPSW Ethernet PHY 1 Default Configuration
        13. 2.1.6.13 GPIO Port Expander
        14. 2.1.6.14 GPIO Mapping
        15. 2.1.6.15 Power
          1. 2.1.6.15.1 Power Requirements
          2. 2.1.6.15.2 Power Input
          3. 2.1.6.15.3 Power Supply
          4. 2.1.6.15.4 Power Sequencing
          5. 2.1.6.15.5 AM62x SoC Power
          6. 2.1.6.15.6 Current Monitoring
        16. 2.1.6.16 AM62x SKEVM User Setup/Configuration
          1. 2.1.6.16.1 EVM DIP Switches
          2. 2.1.6.16.2 Boot Modes
          3. 2.1.6.16.3 User Test LEDs
        17. 2.1.6.17 Expansion Headers
          1. 2.1.6.17.1 PRU Connector
          2. 2.1.6.17.2 User Expansion Connector
          3. 2.1.6.17.3 MCU Connector
        18. 2.1.6.18 Interrupt
        19. 2.1.6.19 I2C Address Mapping
  7. 3Additional Information
    1. 3.1 EVM Revisions and Assembly Variants
    2. 3.2 Known Issues and Modifications
      1. 3.2.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
      2. 3.2.2  Issue 2 - J9 and J10 Header Alignment on E1
      3. 3.2.3  Issue 3 - USB Boot descoped on E1
      4. 3.2.4  Issue 4 - OLDI Connector Orientation and Pinout
      5. 3.2.5  Issue 5 - Bluetooth descoped on E2 EVMs
      6. 3.2.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
      7. 3.2.7  Issue 7 - TEST_POWERDOWN changes
      8. 3.2.8  Issue 8 - MMC1_SDCD spurious interrupts
      9. 3.2.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
      10. 3.2.10 Issue 10 - INA Current Monitor Adress Changes
      11. 3.2.11 Issue 11 - Test Automation I2C Buffer Changes
    3. 3.3 Trademarks
    4.     84
  8. 4Compliance and Certifications
    1. 4.1 EMC, EMI and ESD Compliance
    2.     Regulatory Compliance
  9. 5Revision History
2.1.6.12.2 CPSW Ethernet PHY 1 Default Configuration

The default configuration of the DP83867 is determined using a number of resistor pull-up and pull-down values on specific pins of the PHY. Depending on the values installed, each of the configuration pins can be set to one of four modes by using the pull up and pull down options provided. The AM62x SKEVM uses the 48-pin QFN package which supports the RGMII interface.

The DP83867 PHY uses four level configurations based on resistor strapping which generate four distinct voltages ranges. The resistors are connected to the RX data and control pins which are normally driven by the PHY and are inputs to the processor. The voltage range for each mode is shown below:

Mode 1 - 0 V to 0.3 V

Mode 2 – 0.462 V to 0.6303 V

Mode 3 – 0.7425 V to 0.9372 V

Mode 4 – 2.2902 V to 2.9304 V

Footprint for both pull-up and pull-down is provided on all the strapping pins except LED_0. LED_0 is for Mirror Enable, which is set to mode 1 by default, Mode 4 is not applicable and Mode2, Mode3 option is not desired.

CPSW_RGMII1 port of the AM62x SoC is connected to DP83867 whose configuration is as given below:

PHY ADDR: 00000

Auto_neg: Enabled

ANGsel 10/100/1000

RGMII Clk skew Tx: 0 ns

RGMII Clk skew Rx: 2 ns