SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.1.1 MSS_CTRL_R5SS0_CONTROL Register (Offset = 20h) [reset = 707h]

This register is used to configure R5SS0 in Lock step or Dual core mode. The mode change can be affected only once in a SOC power cycle.

Table 2-3 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D0 0020h

Figure 2-1 MSS_CTRL_R5SS0_CONTROL Name Register

31	30	29	28	27	26	25	24
RESERVED					R5SS0_CONTROL_ROM_WAIT_STATE
NONE					R/W
0h					0h
23	22	21	20	19	18	17	16
RESERVED					R5SS0_CONTROL_RESET_FSM_TRIGGER
NONE					R/W
0h					0h
15	14	13	12	11	10	9	8
RESERVED					R5SS0_CONTROL_LOCK_STEP_SWITCH_WAIT
NONE					R/W
0h					7h
7	6	5	4	3	2	1	0
RESERVED					R5SS0_CONTROL_LOCK_STEP
NONE					R/W
0h					7h

Table 2-4 MSS_CTRL_R5SS0_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:27	RESERVED	NONE	0h	Reserved
26:24	R5SS0_CONTROL_ROM_WAIT_STATE	R/W	0h	Writing 3'b111 enables a single cycle wait state with respect to CR5A_clk for rom access. This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. [because it is a timing issue in this scenario]
23:19	RESERVED	NONE	0h	Reserved
18:16	R5SS0_CONTROL_RESET_FSM_TRIGGER	R/W	0h	Write pulse bit field: Writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit
15:11	RESERVED	NONE	0h	Reserved
10:8	R5SS0_CONTROL_LOCK_STEP_SWITCH_WAIT	R/W	7h	Writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch.
7:3	RESERVED	NONE	0h	Reserved
2:0	R5SS0_CONTROL_LOCK_STEP	R/W	7h	Writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if corresponding R5SS_CONTROL_LOCK_STEP_SWITCH_WAIT is set. Or else the switiching to Dual-core happens on the fly.