SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.103 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_MASK Register

2.2.103.1 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_MASK Register (Offset = 4030h) [reset = 0h]

This register Masks selected interrupt soures from generating MPU Protection Error Interrupt to R5SS0 CORE0 .

Table 2-207 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D0 4030h

Figure 2-103 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_MASK Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED						MPU_PROT_INTR_ERRAGG0_MASK_MPU_HSM_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B1_AHB_PROT_ERR0
NONE						R/W	R/W
0h						0h	0h
15	14	13	12	11	10	9	8
MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A1_AHB_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B0_AHB_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A0_AHB_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_SCRM2SCRP1_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_SCRM2SCRP0_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_QSPI_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_MBOX_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_DTHE_A_PROT_ERR0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B1_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A1_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B0_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A0_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_D_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_C_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_B_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_A_PROT_ERR0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 2-208 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED	NONE	0h	Reserved
17	MPU_PROT_INTR_ERRAGG0_MASK_MPU_HSM_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
16	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B1_AHB_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
15	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A1_AHB_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
14	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B0_AHB_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
13	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A0_AHB_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
12	MPU_PROT_INTR_ERRAGG0_MASK_MPU_SCRM2SCRP1_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
11	MPU_PROT_INTR_ERRAGG0_MASK_MPU_SCRM2SCRP0_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
10	MPU_PROT_INTR_ERRAGG0_MASK_MPU_QSPI_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
9	MPU_PROT_INTR_ERRAGG0_MASK_MPU_MBOX_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
8	MPU_PROT_INTR_ERRAGG0_MASK_MPU_DTHE_A_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
7	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B1_AXIS_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
6	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A1_AXIS_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
5	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5B0_AXIS_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
4	MPU_PROT_INTR_ERRAGG0_MASK_MPU_CR5A0_AXIS_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
3	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_D_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
2	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_C_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
1	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_B_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked
0	MPU_PROT_INTR_ERRAGG0_MASK_MPU_L2_BANK_A_PROT_ERR0	R/W	0h	Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG 1'b1 : Error is Masked 1'b0 : Error is Unmasked