SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.143 MSS_CTRL_PRU-ICSS_PRU1_MBOX_WRITE_DONE Register

2.2.143.1 MSS_CTRL_PRU-ICSS_PRU1_MBOX_WRITE_DONE Register (Offset = 14010h) [reset = 0h]

This register is used by ICSSM PRU1 to generate Mailbox interrupt to Recipent CPU.

Table 2-287 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 4010h

Figure 2-143 MSS_CTRL_PRU-ICSS_PRU1_MBOX_WRITE_DONE Name Register

31	30	29	28	27	26	25	24
RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_7	RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_6
NONE			R/W	NONE			R/W
0h			0h	0h			0h
23	22	21	20	19	18	17	16
RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_5	RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_4
NONE			R/W	NONE			R/W
0h			0h	0h			0h
15	14	13	12	11	10	9	8
RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_3	RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_2
NONE			R/W	NONE			R/W
0h			0h	0h			0h
7	6	5	4	3	2	1	0
RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_1	RESERVED			PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_0
NONE			R/W	NONE			R/W
0h			0h	0h			0h

Table 2-288 MSS_CTRL_PRU-ICSS_PRU1_MBOX_WRITE_DONE Register Field Descriptions

Bit	Field	Type	Reset	Description
31:29	RESERVED	NONE	0h	Reserved
28	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_7	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 7
27:25	RESERVED	NONE	0h	Reserved
24	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_6	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 6
23:21	RESERVED	NONE	0h	Reserved
20	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_5	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 5
19:17	RESERVED	NONE	0h	Reserved
16	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_4	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 4
15:13	RESERVED	NONE	0h	Reserved
12	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_3	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 3
11:9	RESERVED	NONE	0h	Reserved
8	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_2	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 2
7:5	RESERVED	NONE	0h	Reserved
4	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_1	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 1
3:1	RESERVED	NONE	0h	Reserved
0	PRU-ICSS_PRU1_MBOX_WRITE_DONE_PROC_0	R/W	0h	Write pulse bit field: This register should be written once finishing Writing into the mailbox memory of processor 0