SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register enables Core debug reset request to propogate to RCM.
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| Instance Name | Physical Address |
|---|---|
| MSS_RCM | 5320 8018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SYSRST_BY_DBG_RST0_R5B | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SYSRST_BY_DBG_RST0_R5A | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18:16 | SYSRST_BY_DBG_RST0_R5B | R/W | 0h | Writing 3'b111 will block debug reset request from CORE1 toggling reset for CORE1 of respective R5SS |
| 15:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | SYSRST_BY_DBG_RST0_R5A | R/W | 0h | Writing 3'b111 will block debug reset request from CORE0 toggling reset for CORE0 of respective R5SS |