SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.2.22.1 ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_RAW_J Register (Offset = 400h) [reset = 0h]

Raw Status/Set Register for Group A Errors

Offset = Base + (j * 20h); where j = 0 to 2d

Table 5-1035 Instance Table

Instance Name	Physical Address
ESM0	52D0 0400h + formula

Figure 5-515 ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_RAW_J Name Register

Table 5-1036 ESM_PCR_GENERATED_MEMORY_MAP_ERR_GRP_RAW_J Register Field Descriptions

Bit	Field	Type	Reset	Description
31:0	STS	R/W1TS	0h	This is the raw status of the events in group N. Each bit corresponds to event Q where Q = N32+Bit (Example: bit 0 is event N32+0, bit 1 is N*32 + 1 etc). For Level events, the raw status is the event input synchronized to the ESM clock and stored in a multi-bit (for redundancy) internal register. For Pulse events, the raw status is multi-bit (for redundancy) internal register that is set when two of the three edge detection circuits on the redundant event capture a rising edge. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. Read: 1'b0: Inactive 1'b1: Active/Pending Write 1'b1 to set interrupt raw status