SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Control Register. The Control Register contains general control bits for the MCANSS.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCAN0 | 5260 8004h |
| MCAN1 | 5261 8004h |
| MCAN2 | 5262 8004h |
| MCAN3 | 5263 8004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU0 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NU0 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NU0 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NU0 | EXT_TS_CNTR_EN | AUTOWAKEUP | WAKEUPREGEN | DBGSUSP_FREE | NU | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 1h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:7 | NU0 | R | 0h | Reserved |
| 6 | EXT_TS_CNTR_EN | R/W | 0h | External TimeStamp Counter Enable |
| 5 | AUTOWAKEUP | R/W | 0h | Automatic Wakeup Enable |
| 4 | WAKEUPREGEN | R/W | 0h | Wakeup Request Enable |
| 3 | DBGSUSP_FREE | R/W | 1h | 0-Honor Debug Suspend, 1-Disregard debug suspend |
| 2:0 | NU | R | 0h | Reserved |