SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1
Read This First
1. About This Register Addendum
  1. 4
  2. Note on Register Names
  3. Glossary
  4. Trademarks
  5. Export Control Notice
  6. Related Documentation From Texas Instruments
2. 10
3. Support Resources
4. Release History (Register Addendum)
1Memory Map
2Control Module (CTRLMMR) Registers
3Real-time Control Subsystem (CONTROLSS) Registers
4Processor and Accelerator Registers
5System-on-chip (SoC) Registers
6Revision History

5.12.2.68 CFG_TXBTO Register

12.2.68.1 CFG_TXBTO Register (Offset = 2D8h) [reset = 0h]

Tx Buffer Transmission Occurred register. Signals successful transmissions, set when corresponding MCAN_TXBRP flag is cleared. Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of register the MCAN_TXBAR register.

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Table 5-1508 Instance Table

Instance Name	Physical Address
MCAN0	5260 82D8h
MCAN1	5261 82D8h
MCAN2	5262 82D8h
MCAN3	5263 82D8h

Figure 5-744 CFG_TXBTO Name Register

31	30	29	28	27	26	25	24
TO
R
0h
23	22	21	20	19	18	17	16
TO
R
0h
15	14	13	12	11	10	9	8
TO
R
0h
7	6	5	4	3	2	1	0
TO
R
0h

Table 5-1509 CFG_TXBTO Register Field Descriptions

Bit	Field	Type	Reset	Description
31:0	TO	R	0h	Transmission Occurred

31	30	29	28	27	26	25	24
TO
R
0h
23	22	21	20	19	18	17	16
TO
R
0h
15	14	13	12	11	10	9	8
TO
R
0h
7	6	5	4	3	2	1	0
TO
R
0h

31	30	29	28	27	26	25	24
TO
R
0h
23	22	21	20	19	18	17	16
TO
R
0h
15	14	13	12	11	10	9	8
TO
R
0h
7	6	5	4	3	2	1	0
TO
R
0h

31	30	29	28	27	26	25	24
TO
R
0h
23	22	21	20	19	18	17	16
TO
R
0h
15	14	13	12	11	10	9	8
TO
R
0h
7	6	5	4	3	2	1	0
TO
R
0h