SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Eval Register
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| Instance Name | Physical Address |
|---|---|
| EDMA0 | 52A0 1078h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RES69 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RES69 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RES69 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES69 | SET | EVAL | |||||
| R | W | W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RES69 | R | 0h | RESERVE FIELD |
| 1 | SET | W | 0h | Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable [IERn] and status [IPRn]. CPU write of '0' has no effect. |
| 0 | EVAL | W | 0h | Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts [IERn] are still pending [IPRn]. CPU write of '0' has no effect.. |