SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.10.2.13 FSI_TX_CFG_TX_INT_CTRL Register

10.2.13.1 FSI_TX_CFG_TX_INT_CTRL Register (Offset = 20h) [reset = 0h]

Transmit interrupt event control register.

Table 3-1092 Instance Table

Instance Name	Physical Address
FSI_TX0	5028 0020h
FSI_TX1	5028 1020h
FSI_TX2	502A 0020h
FSI_TX3	502A 1020h

Figure 3-514 FSI_TX_CFG_TX_INT_CTRL Name Register

15	14	13	12	11	10	9	8
RESERVED_2				INT2_EN_PING_TO	INT2_EN_BUF_OVERRUN	INT2_EN_BUF_UNDERRUN	INT2_EN_FRAME_DONE
R				R/W	R/W	R/W	R/W
0h				0h	0h	0h	0h
7	6	5	4	3	2	1	0
RESERVED_1				INT1_EN_PING_TO	INT1_EN_BUF_OVERRUN	INT1_EN_BUF_UNDERRUN	INT1_EN_FRAME_DONE
R				R/W	R/W	R/W	R/W
0h				0h	0h	0h	0h

Table 3-1093 FSI_TX_CFG_TX_INT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED_2	R	0h	Reserved
11	INT2_EN_PING_TO	R/W	0h	Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT2.
10	INT2_EN_BUF_OVERRUN	R/W	0h	Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Overrun condition will trigger an interrupt on TX_INT2.
9	INT2_EN_BUF_UNDERRUN	R/W	0h	Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Buffer Underrun condition will trigger an interrupt on TX_INT2.
8	INT2_EN_FRAME_DONE	R/W	0h	Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT2. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT2.
7:4	RESERVED_1	R	0h	Reserved
3	INT1_EN_PING_TO	R/W	0h	Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = The ping timer event will trigger an interrupt on TX_INT1.
2	INT1_EN_BUF_OVERRUN	R/W	0h	Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Overrun condition will trigger an interrupt on TX_INT1.
1	INT1_EN_BUF_UNDERRUN	R/W	0h	Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Buffer Underrun condition will trigger an interrupt on TX_INT1.
0	INT1_EN_FRAME_DONE	R/W	0h	Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h[R/W] = This event will not trigger an interrupt on TX_INT1. 1h[R/W] = A Frame Done event will trigger an interrupt on TX_INT1.