SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
CRC interrupt disable register. Write one to a bit to disable a interrupt.
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| Instance Name | Physical Address |
|---|---|
| MCRC0 | 3500 0020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED5 | CH4_TIMEOUTENR | CH4_UNDERENR | CH4_OVERENR | CH4_CRCFAILENR | RESERVED4 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED4 | CH3_TIMEOUTENR | CH3_UNDERENR | CH3_OVERENR | CH3_CRCFAILENR | RESERVED3 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED3 | CH2_TIMEOUTENR | CH2_UNDERENR | CH2_OVERENR | CH2_CRCFAILENR | RESERVED2 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED2 | CH1_TIMEOUTENR | CH1_UNDERENR | CH1_OVERENR | CH1_CRCFAILENR | RESERVED1 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED5 | R | 0h | |
| 28 | CH4_TIMEOUTENR | R/W | 0h | Channel 4 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable |
| 27 | CH4_UNDERENR | R/W | 0h | Channel 4 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/dis- able]. User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable |
| 26 | CH4_OVERENR | R/W | 0h | Channel 4 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable |
| 25 | CH4_CRCFAILENR | R/W | 0h | Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable |
| 24:21 | RESERVED4 | R | 0h | |
| 20 | CH3_TIMEOUTENR | R/W | 0h | Channel 3 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable |
| 19 | CH3_UNDERENR | R/W | 0h | Channel 3 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/dis- able]. User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable |
| 18 | CH3_OVERENR | R/W | 0h | Channel 3 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable |
| 17 | CH3_CRCFAILENR | R/W | 0h | Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable |
| 16:13 | RESERVED3 | R | 0h | |
| 12 | CH2_TIMEOUTENR | R/W | 0h | Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable |
| 11 | CH2_UNDERENR | R/W | 0h | Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/dis- able]. User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable |
| 10 | CH2_OVERENR | R/W | 0h | Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable |
| 9 | CH2_CRCFAILENR | R/W | 0h | Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable |
| 8:5 | RESERVED2 | R | 0h | |
| 4 | CH1_TIMEOUTENR | R/W | 0h | Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable |
| 3 | CH1_UNDERENR | R/W | 0h | Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/dis- able]. User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable |
| 2 | CH1_OVERENR | R/W | 0h | Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable |
| 1 | CH1_CRCFAILENR | R/W | 0h | Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status [interrupt enable/disable]. User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable |
| 0 | RESERVED1 | R | 0h |