SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Timebase Control selection which source triggers free running counter 0 .
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| WDT0 | 5210 0004h |
| WDT1 | 5210 1004h |
| WDT2 | 5210 2004h |
| WDT3 | 5210 3004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED3 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED3 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED3 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED3 | INC | TBEXT | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED3 | R/W | 0h | Reserved |
| 1 | INC | R/W | 0h | INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode [read]: 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode [write]: 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock |
| 0 | TBEXT | R/W | 0h | TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode [read]: 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode [write]: 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme |