SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Position Counter .
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| Instance Name | Physical Address |
|---|---|
| EQEP0 | 5027 0000h |
| EQEP1 | 5027 1000h |
| EQEP2 | 5027 2000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| QPOSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| QPOSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| QPOSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| QPOSCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | QPOSCNT | R/W | 0h | Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This Register acts as a Read ONLY register while counter is counting up/down. Note: It is recommended to only write to the position counter register [QPOSCNT] during initialization, i.e. when the eQEP position counter is disabled [QPEN bit of QEPCTL is zero]. Once the position counter is enabled [QPEN bit is one], Writing to the eQEP position counter register [QPOSCNT] may cause unexpected results. |