An I2C target device pulls the SCL
line low to push the I2C controller device into the wait state preventing the I2C
controller from transmitting data. This concept is called Clock Stretching.
The I2C supports three different types
of clock stretching:
- Automatic Clock Stretching:
Figure 26-15 shows the timing diagram for automatic clock stretching.
- Target Receiver mode:
- Non-FIFO mode:
I2C clock stretches after receiving 2 bytes from the controller.
- FIFO mode: I2C
clock stretches after receiving 17 bytes from the
controller.
- Target Transmitter mode:
I2C clock stretches, if I2C transmit buffer is empty
Note: Automatic Clock
Stretching is enabled by default and cannot be disabled.
- Extended Automatic Clock
Stretching: Figure 26-16 shows the timing diagram for extended automatic clock stretching.
Extended Automatic Clock
Stretching can be enabled by setting I2CEMDR. ECS = 1. Once this feature is
enabled, I2C hardware automatically does clock stretching by pulling the SCL
line low after every ACK/NACK cycle and generates an I2C interrupt. Inside
the I2C ISR, I2CSTR.SCL_ECS is set to 1 to release the I2C from clock
stretching.
Note: Extended
Automatic Clock Stretching is disabled by default and can be enabled by
setting I2CEMDR.ECS = 1.
- Manual Clock Stretching:
Manual Clock Stretching can be enabled by setting I2CEMDR.MCS = 1 within an ISR
routine. Once this feature is enabled, I2C hardware can be configured to
manually do clock stretching by pulling the SCL line low after specific ACK/NACK
cycles. I2C module then performs housekeeping and executes normal ISR sequence
steps before disabling MCS by setting I2CEMDR.MCS = 0.
Note: Manual Clock Stretching is disabled by default and can
be enabled by setting I2CEMDR.MCS = 1. Timing requirements for this type of
clock stretching are not provided due to dependency on user configuration
and application.