SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 3-279 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses not listed in Table 3-279 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | DxLOCK | Dedicated RAM Config Lock Register | EALLOW | Go |
2h | DxCOMMIT | Dedicated RAM Config Lock Commit Register | EALLOW | Go |
8h | DxACCPROT0 | Dedicated RAM Config Register | EALLOW | Go |
Ah | DxACCPROT1 | Dedicated RAM Config Register | EALLOW | Go |
10h | DxTEST | Dedicated RAM TEST Register | Go | |
12h | DxINIT | Dedicated RAM Init Register | EALLOW | Go |
14h | DxINITDONE | Dedicated RAM InitDone Status Register | Go | |
16h | DxRAMTEST_LOCK | Lock register to Dx RAM TEST registers | Go | |
20h | LSxLOCK | Local Shared RAM Config Lock Register | EALLOW | Go |
22h | LSxCOMMIT | Local Shared RAM Config Lock Commit Register | EALLOW | Go |
24h | LSxMSEL | Local Shared RAM Controller Sel Register | EALLOW | Go |
26h | LSxCLAPGM | Local Shared RAM Prog/Exe control Register | EALLOW | Go |
28h | LSxACCPROT0 | Local Shared RAM Config Register 0 | EALLOW | Go |
2Ah | LSxACCPROT1 | Local Shared RAM Config Register 1 | EALLOW | Go |
2Ch + formula | LSxACCPROT2_y | Local Shared RAM Config Register 2 | EALLOW | Go |
30h | LSxTEST | Local Shared RAM TEST Register | Go | |
32h | LSxINIT | Local Shared RAM Init Register | EALLOW | Go |
34h | LSxINITDONE | Local Shared RAM InitDone Status Register | Go | |
36h | LSxRAMTEST_LOCK | Lock register to LSx RAM TEST registers | Go | |
40h | GSxLOCK | Global Shared RAM Config Lock Register | EALLOW | Go |
42h | GSxCOMMIT | Global Shared RAM Config Lock Commit Register | EALLOW | Go |
48h | GSxACCPROT0 | Global Shared RAM Config Register 0 | EALLOW | Go |
50h | GSxTEST | Global Shared RAM TEST Register | Go | |
52h | GSxINIT | Global Shared RAM Init Register | EALLOW | Go |
54h | GSxINITDONE | Global Shared RAM InitDone Status Register | Go | |
56h | GSxRAMTEST_LOCK | Lock register to GSx RAM TEST registers | Go | |
60h | MSGxLOCK | Message RAM Config Lock Register | EALLOW | Go |
62h | MSGxCOMMIT | Message RAM Config Lock Commit Register | EALLOW | Go |
70h | MSGxTEST | Message RAM TEST Register | Go | |
72h | MSGxINIT | Message RAM Init Register | EALLOW | Go |
74h | MSGxINITDONE | Message RAM InitDone Status Register | Go | |
76h | MSGxRAMTEST_LOCK | Lock register for MSGx RAM TEST Register | Go | |
A0h | ROM_LOCK | ROM Config Lock Register | Go | |
A2h | ROM_TEST | ROM TEST Register | Go | |
A4h | ROM_FORCE_ERROR | ROM Force Error register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-280 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
DxLOCK is shown in Figure 3-249 and described in Table 3-281.
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Dedicated RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_PIEVECT | RESERVED | RESERVED | LOCK_M1 | LOCK_M0 | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | LOCK_PIEVECT | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for PIEVECT RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LOCK_M1 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
0 | LOCK_M0 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
DxCOMMIT is shown in Figure 3-250 and described in Table 3-282.
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Dedicated RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_PIEVECT | RESERVED | RESERVED | COMMIT_M1 | COMMIT_M0 | ||
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | COMMIT_PIEVECT | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, initialization control and test register fields for PIEVECT RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | COMMIT_M1 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_M0 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
DxACCPROT0 is shown in Figure 3-251 and described in Table 3-283.
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Dedicated RAM Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_M1 | FETCHPROT_M1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_M0 | FETCHPROT_M0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23-18 | RESERVED | R | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_M1 | R/W | 0h | CPU WR Protection For M1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
8 | FETCHPROT_M1 | R/W | 0h | Fetch Protection For M1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_M0 | R/W | 0h | CPU WR Protection For M0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
0 | FETCHPROT_M0 | R/W | 0h | Fetch Protection For M0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
DxACCPROT1 is shown in Figure 3-252 and described in Table 3-284.
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Dedicated RAM Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_PIEVECT | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_PIEVECT | R/W | 0h | CPU Write Protection For PIEVECT RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
DxTEST is shown in Figure 3-253 and described in Table 3-285.
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Dedicated RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEST_PIEVECT | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | TEST_M1 | TEST_M0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9-8 | TEST_PIEVECT | R/W | 0h | Selects the defferent modes for PIEVECT RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | TEST_M1 | R/W | 0h | Selects the defferent modes for M1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | TEST_M0 | R/W | 0h | Selects the defferent modes for M0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
DxINIT is shown in Figure 3-254 and described in Table 3-286.
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Dedicated RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_PIEVECT | RESERVED | RESERVED | INIT_M1 | INIT_M0 | ||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | INIT_PIEVECT | R-0/W1S | 0h | RAM Initialization control for PIEVECT RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | INIT_M1 | R-0/W1S | 0h | RAM Initialization control for M1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_M0 | R-0/W1S | 0h | RAM Initialization control for M0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
DxINITDONE is shown in Figure 3-255 and described in Table 3-287.
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Dedicated RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_PIEVECT | RESERVED | RESERVED | INITDONE_M1 | INITDONE_M0 | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | INITDONE_PIEVECT | R | 0h | RAM Initialization status for PIEVECT RAM: 0: RAM Initialization has completed. 1: RAM Initialization has completed. Reset type: SYSRSn |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | INITDONE_M1 | R | 0h | RAM Initialization status for M1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization has completed. Reset type: SYSRSn |
0 | INITDONE_M0 | R | 0h | RAM Initialization status for M0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
DxRAMTEST_LOCK is shown in Figure 3-256 and described in Table 3-288.
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Lock register to Dx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIEVECT | RESERVED | RESERVED | M1 | M0 | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-5 | RESERVED | R | 0h | Reserved |
4 | PIEVECT | R/W | 0h | 0: Allows writes to DxTEST.TEST_PIEVECT field. 1: Blocks writes to DxTEST.TEST_PIEVECT field Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | M1 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M1 field. 1: Blocks writes to DxTEST.TEST_M1 field Reset type: SYSRSn |
0 | M0 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M0 field. 1: Blocks writes to DxTEST.TEST_M0 field Reset type: SYSRSn |
LSxLOCK is shown in Figure 3-257 and described in Table 3-289.
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Local Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LOCK_LS9 | LOCK_LS8 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK_LS7 | LOCK_LS6 | LOCK_LS5 | LOCK_LS4 | LOCK_LS3 | LOCK_LS2 | LOCK_LS1 | LOCK_LS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | LOCK_LS9 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS9 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
8 | LOCK_LS8 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS8 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
7 | LOCK_LS7 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS7 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
6 | LOCK_LS6 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS6 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
5 | LOCK_LS5 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS5 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
4 | LOCK_LS4 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS4 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
3 | LOCK_LS3 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS3 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
2 | LOCK_LS2 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS2 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
1 | LOCK_LS1 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
0 | LOCK_LS0 | R/W | 0h | Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
LSxCOMMIT is shown in Figure 3-258 and described in Table 3-290.
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Local Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COMMIT_LS9 | COMMIT_LS8 | |||||
R-0h | R/WSonce-0h | R/WSonce-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMMIT_LS7 | COMMIT_LS6 | COMMIT_LS5 | COMMIT_LS4 | COMMIT_LS3 | COMMIT_LS2 | COMMIT_LS1 | COMMIT_LS0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | COMMIT_LS9 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS9 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
8 | COMMIT_LS8 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS8 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
7 | COMMIT_LS7 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS7 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
6 | COMMIT_LS6 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS6 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
5 | COMMIT_LS5 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS5 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
4 | COMMIT_LS4 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS4 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
3 | COMMIT_LS3 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS3 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_LS2 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS2 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_LS1 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_LS0 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, program or data memory select, initialization control and test register fields for LS0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
LSxMSEL is shown in Figure 3-259 and described in Table 3-291.
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Local Shared RAM Controller Sel Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MSEL_LS9 | MSEL_LS8 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSEL_LS7 | MSEL_LS6 | MSEL_LS5 | MSEL_LS4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSEL_LS3 | MSEL_LS2 | MSEL_LS1 | MSEL_LS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-18 | MSEL_LS9 | R/W | 0h | Controller Select for LS9 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
17-16 | MSEL_LS8 | R/W | 0h | Controller Select for LS8 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
15-14 | MSEL_LS7 | R/W | 0h | Controller Select for LS7 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
13-12 | MSEL_LS6 | R/W | 0h | Controller Select for LS6 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
11-10 | MSEL_LS5 | R/W | 0h | Controller Select for LS5 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
9-8 | MSEL_LS4 | R/W | 0h | Controller Select for LS4 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
7-6 | MSEL_LS3 | R/W | 0h | Controller Select for LS3 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
5-4 | MSEL_LS2 | R/W | 0h | Controller Select for LS2 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
3-2 | MSEL_LS1 | R/W | 0h | Controller Select for LS1 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
1-0 | MSEL_LS0 | R/W | 0h | Controller Select for LS0 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
LSxCLAPGM is shown in Figure 3-260 and described in Table 3-292.
Return to the Summary Table.
Local Shared RAM Prog/Exe control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLAPGM_LS9 | CLAPGM_LS8 | |||||
R-0h | R/W-1h | R/W-1h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLAPGM_LS7 | CLAPGM_LS6 | CLAPGM_LS5 | CLAPGM_LS4 | CLAPGM_LS3 | CLAPGM_LS2 | CLAPGM_LS1 | CLAPGM_LS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | CLAPGM_LS9 | R/W | 1h | Selects LS9 RAM as program vs data memory for CLA: 0: Reserved. 1: CLA Program memory. Reset type: SYSRSn |
8 | CLAPGM_LS8 | R/W | 1h | Selects LS8 RAM as program vs data memory for CLA: 0: Reserved. 1: CLA Program memory. Reset type: SYSRSn |
7 | CLAPGM_LS7 | R/W | 0h | Selects LS7 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
6 | CLAPGM_LS6 | R/W | 0h | Selects LS6 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
5 | CLAPGM_LS5 | R/W | 0h | Selects LS5 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
4 | CLAPGM_LS4 | R/W | 0h | Selects LS4 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
3 | CLAPGM_LS3 | R/W | 0h | Selects LS3 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
2 | CLAPGM_LS2 | R/W | 0h | Selects LS2 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
1 | CLAPGM_LS1 | R/W | 0h | Selects LS1 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
0 | CLAPGM_LS0 | R/W | 0h | Selects LS0 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
LSxACCPROT0 is shown in Figure 3-261 and described in Table 3-293.
Return to the Summary Table.
Local Shared RAM Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_LS3 | FETCHPROT_LS3 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_LS2 | FETCHPROT_LS2 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS1 | FETCHPROT_LS1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS0 | FETCHPROT_LS0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_LS3 | R/W | 0h | CPU WR Protection For LS3 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_LS3 | R/W | 0h | Fetch Protection For LS3 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_LS2 | R/W | 0h | CPU WR Protection For LS2 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_LS2 | R/W | 0h | Fetch Protection For LS2 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS1 | R/W | 0h | CPU WR Protection For LS1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS1 | R/W | 0h | Fetch Protection For LS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS0 | R/W | 0h | CPU WR Protection For LS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS0 | R/W | 0h | Fetch Protection For LS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxACCPROT1 is shown in Figure 3-262 and described in Table 3-294.
Return to the Summary Table.
Local Shared RAM Config Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_LS7 | FETCHPROT_LS7 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_LS6 | FETCHPROT_LS6 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS5 | FETCHPROT_LS5 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS4 | FETCHPROT_LS4 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_LS7 | R/W | 0h | CPU WR Protection For LS7 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_LS7 | R/W | 0h | Fetch Protection For LS7 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_LS6 | R/W | 0h | CPU WR Protection For LS6 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_LS6 | R/W | 0h | Fetch Protection For LS6 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS5 | R/W | 0h | CPU WR Protection For LS5 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS5 | R/W | 0h | Fetch Protection For LS5 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS4 | R/W | 0h | CPU WR Protection For LS4 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS4 | R/W | 0h | Fetch Protection For LS4 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxACCPROT2_y is shown in Figure 3-263 and described in Table 3-295.
Return to the Summary Table.
Local Shared RAM Config Register 2
Offset = 2Ch + (y * 2h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS9 | FETCHPROT_LS9 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS8 | FETCHPROT_LS8 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS9 | R/W | 0h | CPU WR Protection For LS9 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS9 | R/W | 0h | Fetch Protection For LS9 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS8 | R/W | 0h | CPU WR Protection For LS8 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS8 | R/W | 0h | Fetch Protection For LS8 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxTEST is shown in Figure 3-264 and described in Table 3-296.
Return to the Summary Table.
Local Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TEST_LS9 | TEST_LS8 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEST_LS7 | TEST_LS6 | TEST_LS5 | TEST_LS4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_LS3 | TEST_LS2 | TEST_LS1 | TEST_LS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-18 | TEST_LS9 | R/W | 0h | Selects the defferent modes for LS9 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
17-16 | TEST_LS8 | R/W | 0h | Selects the defferent modes for LS8 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
15-14 | TEST_LS7 | R/W | 0h | Selects the defferent modes for LS7 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
13-12 | TEST_LS6 | R/W | 0h | Selects the defferent modes for LS6 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
11-10 | TEST_LS5 | R/W | 0h | Selects the defferent modes for LS5 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
9-8 | TEST_LS4 | R/W | 0h | Selects the defferent modes for LS4 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
7-6 | TEST_LS3 | R/W | 0h | Selects the defferent modes for LS3 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
5-4 | TEST_LS2 | R/W | 0h | Selects the defferent modes for LS2 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
3-2 | TEST_LS1 | R/W | 0h | Selects the defferent modes for LS1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | TEST_LS0 | R/W | 0h | Selects the defferent modes for LS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
LSxINIT is shown in Figure 3-265 and described in Table 3-297.
Return to the Summary Table.
Local Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INIT_LS9 | INIT_LS8 | |||||
R-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INIT_LS7 | INIT_LS6 | INIT_LS5 | INIT_LS4 | INIT_LS3 | INIT_LS2 | INIT_LS1 | INIT_LS0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | INIT_LS9 | R-0/W1S | 0h | RAM Initialization control for LS9 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
8 | INIT_LS8 | R-0/W1S | 0h | RAM Initialization control for LS8 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
7 | INIT_LS7 | R-0/W1S | 0h | RAM Initialization control for LS7 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
6 | INIT_LS6 | R-0/W1S | 0h | RAM Initialization control for LS6 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
5 | INIT_LS5 | R-0/W1S | 0h | RAM Initialization control for LS5 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | INIT_LS4 | R-0/W1S | 0h | RAM Initialization control for LS4 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | INIT_LS3 | R-0/W1S | 0h | RAM Initialization control for LS3 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_LS2 | R-0/W1S | 0h | RAM Initialization control for LS2 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_LS1 | R-0/W1S | 0h | RAM Initialization control for LS1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_LS0 | R-0/W1S | 0h | RAM Initialization control for LS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
LSxINITDONE is shown in Figure 3-266 and described in Table 3-298.
Return to the Summary Table.
Local Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INITDONE_LS9 | INITDONE_LS8 | |||||
R-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | INITDONE_LS1 | INITDONE_LS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | INITDONE_LS9 | R | 0h | RAM Initialization status for LS9 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
8 | INITDONE_LS8 | R | 0h | RAM Initialization status for LS8 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | INITDONE_LS1 | R | 0h | RAM Initialization status for LS1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_LS0 | R | 0h | RAM Initialization status for LS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
LSxRAMTEST_LOCK is shown in Figure 3-267 and described in Table 3-299.
Return to the Summary Table.
Lock register to LSx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||||||||||
R-0/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LS9 | LS8 | LS7 | LS6 | LS5 | LS4 | LS3 | LS2 | LS1 | LS0 | |||||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | LS9 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS9 field. 1: Blocks writes to LSxTEST.TEST_LS9 field. Reset type: SYSRSn |
8 | LS8 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS8 field. 1: Blocks writes to LSxTEST.TEST_LS8 field. Reset type: SYSRSn |
7 | LS7 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS7 field. 1: Blocks writes to LSxTEST.TEST_LS7 field. Reset type: SYSRSn |
6 | LS6 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS6 field. 1: Blocks writes to LSxTEST.TEST_LS6 field. Reset type: SYSRSn |
5 | LS5 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS5 field. 1: Blocks writes to LSxTEST.TEST_LS5 field. Reset type: SYSRSn |
4 | LS4 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS4 field. 1: Blocks writes to LSxTEST.TEST_LS4 field. Reset type: SYSRSn |
3 | LS3 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS3 field. 1: Blocks writes to LSxTEST.TEST_LS3 field. Reset type: SYSRSn |
2 | LS2 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS2 field. 1: Blocks writes to LSxTEST.TEST_LS2 field. Reset type: SYSRSn |
1 | LS1 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS1 field. 1: Blocks writes to LSxTEST.TEST_LS1 field. Reset type: SYSRSn |
0 | LS0 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS0 field. 1: Blocks writes to LSxTEST.TEST_LS0 field. Reset type: SYSRSn |
GSxLOCK is shown in Figure 3-268 and described in Table 3-300.
Return to the Summary Table.
Global Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | LOCK_GS3 | LOCK_GS2 | LOCK_GS1 | LOCK_GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | LOCK_GS3 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for GS3 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
2 | LOCK_GS2 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for GS2 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
1 | LOCK_GS1 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for GS1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
0 | LOCK_GS0 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for GS0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed. 1: Write to ACCPROT, INIT and MSEL fields are blocked. Reset type: SYSRSn |
GSxCOMMIT is shown in Figure 3-269 and described in Table 3-301.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | COMMIT_GS3 | COMMIT_GS2 | COMMIT_GS1 | COMMIT_GS0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R/WSonce | 0h | Reserved |
14 | RESERVED | R/WSonce | 0h | Reserved |
13 | RESERVED | R/WSonce | 0h | Reserved |
12 | RESERVED | R/WSonce | 0h | Reserved |
11 | RESERVED | R/WSonce | 0h | Reserved |
10 | RESERVED | R/WSonce | 0h | Reserved |
9 | RESERVED | R/WSonce | 0h | Reserved |
8 | RESERVED | R/WSonce | 0h | Reserved |
7 | RESERVED | R/WSonce | 0h | Reserved |
6 | RESERVED | R/WSonce | 0h | Reserved |
5 | RESERVED | R/WSonce | 0h | Reserved |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | COMMIT_GS3 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, initialization control and test register fields for GS3 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_GS2 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, initialization control and test register fields for GS2 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_GS1 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, initialization control and test register fields for GS1 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_GS0 | R/WSonce | 0h | Permanently Locks the write to access protection, controller select, initialization control and test register fields for GS0 RAM: 0: Write to ACCPROT, INIT and MSEL fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, INIT and MSEL fields are permanently blocked. Reset type: SYSRSn |
GSxACCPROT0 is shown in Figure 3-270 and described in Table 3-302.
Return to the Summary Table.
Global Shared RAM Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | NPU_WRPROT_GS3 | DMAWRPROT_GS3 | CPUWRPROT_GS3 | FETCHPROT_GS3 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NPU_WRPROT_GS2 | DMAWRPROT_GS2 | CPUWRPROT_GS2 | FETCHPROT_GS2 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NPU_WRPROT_GS1 | DMAWRPROT_GS1 | CPUWRPROT_GS1 | FETCHPROT_GS1 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NPU_WRPROT_GS0 | DMAWRPROT_GS0 | CPUWRPROT_GS0 | FETCHPROT_GS0 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27 | NPU_WRPROT_GS3 | R/W | 0h | NPU WR Protection For GS3 RAM: 0: NPU Writes are allowed. 1: NPU Writes are blocked. Reset type: SYSRSn |
26 | DMAWRPROT_GS3 | R/W | 0h | DMA WR Protection For GS3 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS3 | R/W | 0h | CPU WR Protection For GS3 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS3 | R/W | 0h | Fetch Protection For GS3 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-20 | RESERVED | R | 0h | Reserved |
19 | NPU_WRPROT_GS2 | R/W | 0h | NPU WR Protection For GS2 RAM: 0: NPU Writes are allowed. 1: NPU Writes are blocked. Reset type: SYSRSn |
18 | DMAWRPROT_GS2 | R/W | 0h | DMA WR Protection For GS2 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS2 | R/W | 0h | CPU WR Protection For GS2 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS2 | R/W | 0h | Fetch Protection For GS2 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-12 | RESERVED | R | 0h | Reserved |
11 | NPU_WRPROT_GS1 | R/W | 0h | NPU WR Protection For GS1 RAM: 0: NPU Writes are allowed. 1: NPU Writes are blocked. Reset type: SYSRSn |
10 | DMAWRPROT_GS1 | R/W | 0h | DMA WR Protection For GS1 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS1 | R/W | 0h | CPU WR Protection For GS1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS1 | R/W | 0h | Fetch Protection For GS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-4 | RESERVED | R | 0h | Reserved |
3 | NPU_WRPROT_GS0 | R/W | 0h | NPU WR Protection For GS0 RAM: 0: NPU Writes are allowed. 1: NPU Writes are blocked. Reset type: SYSRSn |
2 | DMAWRPROT_GS0 | R/W | 0h | DMA WR Protection For GS0 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS0 | R/W | 0h | CPU WR Protection For GS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS0 | R/W | 0h | Fetch Protection For GS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxTEST is shown in Figure 3-271 and described in Table 3-303.
Return to the Summary Table.
Global Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_GS3 | TEST_GS2 | TEST_GS1 | TEST_GS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | TEST_GS3 | R/W | 0h | Selects the defferent modes for GS3 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
5-4 | TEST_GS2 | R/W | 0h | Selects the defferent modes for GS2 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
3-2 | TEST_GS1 | R/W | 0h | Selects the defferent modes for GS1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | TEST_GS0 | R/W | 0h | Selects the defferent modes for GS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
GSxINIT is shown in Figure 3-272 and described in Table 3-304.
Return to the Summary Table.
Global Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | INIT_GS3 | INIT_GS2 | INIT_GS1 | INIT_GS0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R-0/W1S | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | INIT_GS3 | R-0/W1S | 0h | RAM Initialization control for GS3 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_GS2 | R-0/W1S | 0h | RAM Initialization control for GS2 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_GS1 | R-0/W1S | 0h | RAM Initialization control for GS1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_GS0 | R-0/W1S | 0h | RAM Initialization control for GS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
GSxINITDONE is shown in Figure 3-273 and described in Table 3-305.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | INITDONE_GS3 | INITDONE_GS2 | INITDONE_GS1 | INITDONE_GS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | INITDONE_GS3 | R | 0h | RAM Initialization status for GS3 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
2 | INITDONE_GS2 | R | 0h | RAM Initialization status for GS2 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_GS1 | R | 0h | RAM Initialization status for GS1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_GS0 | R | 0h | RAM Initialization status for GS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
GSxRAMTEST_LOCK is shown in Figure 3-274 and described in Table 3-306.
Return to the Summary Table.
Lock register to GSx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | GS3 | GS2 | GS1 | GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | GS3 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS3 field. 1: Blocks writes to GSxTEST.TEST_GS3 field. Reset type: SYSRSn |
2 | GS2 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS2 field. 1: Blocks writes to GSxTEST.TEST_GS2 field. Reset type: SYSRSn |
1 | GS1 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS1 field. 1: Blocks writes to GSxTEST.TEST_GS1 field. Reset type: SYSRSn |
0 | GS0 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS0 field. 1: Blocks writes to GSxTEST.TEST_GS0 field. Reset type: SYSRSn |
MSGxLOCK is shown in Figure 3-275 and described in Table 3-307.
Return to the Summary Table.
Message RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_DMATOCLA1 | LOCK_CLA1TODMA | RESERVED | RESERVED | LOCK_CLA1TOCPU | LOCK_CPUTOCLA1 | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | LOCK_DMATOCLA1 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test for DMATOCLA1 RAM: 0: Write to TEST, INIT fields are allowed. 1: Write to TEST, INIT fields are blocked. Reset type: SYSRSn |
5 | LOCK_CLA1TODMA | R/W | 0h | Locks the write to access protection, controller select, initialization control and test for CLA1TODMA RAM: 0: Write to TEST, INIT fields are allowed. 1: Write to TEST, INIT fields are blocked. Reset type: SYSRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | LOCK_CLA1TOCPU | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for CLA1TOCPU RAM: 0: Write to TEST, INIT fields are allowed. 1: Write to TEST, INIT fields are blocked. Reset type: SYSRSn |
1 | LOCK_CPUTOCLA1 | R/W | 0h | Locks the write to access protection, controller select, initialization control and test register fields for CPUTOCLA1 RAM: 0: Write to TEST, INIT fields are allowed. 1: Write to TEST, INIT fields are blocked. Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
MSGxCOMMIT is shown in Figure 3-276 and described in Table 3-308.
Return to the Summary Table.
Message RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_DMATOCLA1 | COMMIT_CLA1TODMA | RESERVED | RESERVED | COMMIT_CLA1TOCPU | COMMIT_CPUTOCLA1 | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R/WSonce | 0h | Reserved |
10 | RESERVED | R/WSonce | 0h | Reserved |
9 | RESERVED | R/WSonce | 0h | Reserved |
8 | RESERVED | R/WSonce | 0h | Reserved |
7 | RESERVED | R/WSonce | 0h | Reserved |
6 | COMMIT_DMATOCLA1 | R/WSonce | 0h | Locks the write to access protection, controller select, initialization control and test register fields for DMATOCLA1 RAM: 0: Write to TEST, INIT fields are allowed based on value of corresponding lock field in MSGxLOCK register. 1: Write to TEST, INIT fields are permanently blocked. Reset type: SYSRSn |
5 | COMMIT_CLA1TODMA | R/WSonce | 0h | Locks the write to access protection, controller select, initialization control and test register fields for CLA1TODMA RAM: 0: Write to TEST, INIT fields are allowed based on value of corresponding lock field in MSGxLOCK register. 1: Write to TEST, INIT fields are permanently blocked. Reset type: SYSRSn |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | COMMIT_CLA1TOCPU | R/WSonce | 0h | Locks the write to access protection, controller select, initialization control and test register fields for CLA1TOCPU RAM: 0: Write to TEST, INIT fields are allowed based on value of corresponding lock field in MSGxLOCK register. 1: Write to TEST, INIT fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_CPUTOCLA1 | R/WSonce | 0h | Locks the write to access protection, controller select, initialization control and test register fields for CPUTOCLA1 RAM: 0: Write to TEST, INIT fields are allowed based on value of corresponding lock field in MSGxLOCK register. 1: Write to TEST, INIT fields are permanently blocked. Reset type: SYSRSn |
0 | RESERVED | R/WSonce | 0h | Reserved |
MSGxTEST is shown in Figure 3-277 and described in Table 3-309.
Return to the Summary Table.
Message RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEST_DMATOCLA1 | TEST_CLA1TODMA | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_CLA1TOCPU | TEST_CPUTOCLA1 | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | TEST_DMATOCLA1 | R/W | 0h | Selects the defferent modes for DMATOCLA1 MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
11-10 | TEST_CLA1TODMA | R/W | 0h | Selects the defferent modes for CLA1TODMA MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | TEST_CLA1TOCPU | R/W | 0h | Selects the defferent modes for CLA1TOCPU MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
3-2 | TEST_CPUTOCLA1 | R/W | 0h | Selects the defferent modes for CPUTOCLA1 MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Same as functional mode, but interrupt/NMI is not generated on error. Note: Any non zero value would enable CPU writes over-riding write access protection if any and will not generate a access protection violation. Reset type: SYSRSn |
1-0 | RESERVED | R/W | 0h | Reserved |
MSGxINIT is shown in Figure 3-278 and described in Table 3-310.
Return to the Summary Table.
Message RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_DMATOCLA1 | INIT_CLA1TODMA | RESERVED | RESERVED | INIT_CLA1TOCPU | INIT_CPUTOCLA1 | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | INIT_DMATOCLA1 | R-0/W1S | 0h | RAM Initialization control for DMATOCLA1 MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
5 | INIT_CLA1TODMA | R-0/W1S | 0h | RAM Initialization control for CLA1TODMA MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | INIT_CLA1TOCPU | R-0/W1S | 0h | RAM Initialization control for CLA1TOCPU MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_CPUTOCLA1 | R-0/W1S | 0h | RAM Initialization control for CPUTOCLA1 MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | RESERVED | R-0/W1S | 0h | Reserved |
MSGxINITDONE is shown in Figure 3-279 and described in Table 3-311.
Return to the Summary Table.
Message RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_DMATOCLA1 | INITDONE_CLA1TODMA | RESERVED | RESERVED | INITDONE_CLA1TOCPU | INITDONE_CPUTOCLA1 | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | INITDONE_DMATOCLA1 | R | 0h | RAM Initialization status for DMATOCLA1 MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
5 | INITDONE_CLA1TODMA | R | 0h | RAM Initialization status for CLA1TODMA MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | INITDONE_CLA1TOCPU | R | 0h | RAM Initialization status for CLA1TOCPU MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_CPUTOCLA1 | R | 0h | RAM Initialization status for CPUTOCLA1 MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
MSGxRAMTEST_LOCK is shown in Figure 3-280 and described in Table 3-312.
Return to the Summary Table.
Lock register for MSGx RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMATOCLA1 | CLA1TODMA | RESERVED | RESERVED | CLA1TOCPU | CPUTOCLA1 | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | DMATOCLA1 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_DMATOCLA1 field 1: Blocks writes to MSGxTEST.TEST_DMATOCLA1 field Reset type: SYSRSn |
5 | CLA1TODMA | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CLA1TODMA field 1: Blocks writes to MSGxTEST.TEST_CLA1TODMA field Reset type: SYSRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | CLA1TOCPU | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CLA1TOCPU field 1: Blocks writes to MSGxTEST.TEST_CLA1TOCPU field Reset type: SYSRSn |
1 | CPUTOCLA1 | R/W | 0h | 0: Allows writes to MSGxTEST.TEST_CPUTOCLA1 field 1: Blocks writes to MSGxTEST.TEST_CPUTOCLA1 field Reset type: SYSRSn |
0 | RESERVED | R/W | 0h | Reserved |
ROM_LOCK is shown in Figure 3-281 and described in Table 3-313.
Return to the Summary Table.
ROM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | LOCK_CLADATAROM | LOCK_SECUREROM | LOCK_BOOTROM | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | LOCK_CLADATAROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of CLADATAROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
1 | LOCK_SECUREROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of SECUREROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
0 | LOCK_BOOTROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of BOOTROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
ROM_TEST is shown in Figure 3-282 and described in Table 3-314.
Return to the Summary Table.
ROM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_CLADATAROM | TEST_SECUREROM | TEST_BOOTROM | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | TEST_CLADATAROM | R/W | 0h | Selects the different modes for CLADATAROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
3-2 | TEST_SECUREROM | R/W | 0h | Selects the different modes for SECUREROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
1-0 | TEST_BOOTROM | R/W | 0h | Selects the different modes for BOOTROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
ROM_FORCE_ERROR is shown in Figure 3-283 and described in Table 3-315.
Return to the Summary Table.
ROM Force Error register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | FORCE_CLADATAROM_ERROR | FORCE_SECUREROM_ERROR | FORCE_BOOTROM_ERROR | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | FORCE_CLADATAROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |
1 | FORCE_SECUREROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |
0 | FORCE_BOOTROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |