SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 3-34 lists the memory-mapped registers for the PIE_CTRL_REGS registers. All register offset addresses not listed in Table 3-34 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | PIECTRL | ePIE Control Register | Go | |
1h | PIEACK | Interrupt Acknowledge Register | Go | |
2h | PIEIER1 | Interrupt Group 1 Enable Register | Go | |
3h | PIEIFR1 | Interrupt Group 1 Flag Register | Go | |
4h | PIEIER2 | Interrupt Group 2 Enable Register | Go | |
5h | PIEIFR2 | Interrupt Group 2 Flag Register | Go | |
6h | PIEIER3 | Interrupt Group 3 Enable Register | Go | |
7h | PIEIFR3 | Interrupt Group 3 Flag Register | Go | |
8h | PIEIER4 | Interrupt Group 4 Enable Register | Go | |
9h | PIEIFR4 | Interrupt Group 4 Flag Register | Go | |
Ah | PIEIER5 | Interrupt Group 5 Enable Register | Go | |
Bh | PIEIFR5 | Interrupt Group 5 Flag Register | Go | |
Ch | PIEIER6 | Interrupt Group 6 Enable Register | Go | |
Dh | PIEIFR6 | Interrupt Group 6 Flag Register | Go | |
Eh | PIEIER7 | Interrupt Group 7 Enable Register | Go | |
Fh | PIEIFR7 | Interrupt Group 7 Flag Register | Go | |
10h | PIEIER8 | Interrupt Group 8 Enable Register | Go | |
11h | PIEIFR8 | Interrupt Group 8 Flag Register | Go | |
12h | PIEIER9 | Interrupt Group 9 Enable Register | Go | |
13h | PIEIFR9 | Interrupt Group 9 Flag Register | Go | |
14h | PIEIER10 | Interrupt Group 10 Enable Register | Go | |
15h | PIEIFR10 | Interrupt Group 10 Flag Register | Go | |
16h | PIEIER11 | Interrupt Group 11 Enable Register | Go | |
17h | PIEIFR11 | Interrupt Group 11 Flag Register | Go | |
18h | PIEIER12 | Interrupt Group 12 Enable Register | Go | |
19h | PIEIFR12 | Interrupt Group 12 Flag Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-35 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value |
PIECTRL is shown in Figure 3-26 and described in Table 3-36.
Return to the Summary Table.
ePIE Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PIEVECT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PIEVECT | ENPIE | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | PIEVECT | R | 0h | These bits indicate the vector address of the vector fetched from the ePIE vector table. The least significant bit of the address is ignored and only bits 1 to 15 of the address are shown. The vector value can be read by the user to determine which interrupt generated the vector fetch. Note: When a NMI is serviced, the PIEVECT bit-field does not reflect the vector as it does for other interrupts. Reset type: SYSRSn |
0 | ENPIE | R/W | 0h | Enable vector fetching from ePIE block. This bit must be set to 1 for peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR, PIEIER) can be accessed even when the ePIE block is disabled. Reset type: SYSRSn |
PIEACK is shown in Figure 3-27 and described in Table 3-37.
Return to the Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is set. This prevents other interrupts in that group from propagating to the CPU while the first interrupt is handled. Writing a 1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to propagate. ISRs for PIE interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ACK12 | ACK11 | ACK10 | ACK9 | |||
R-0-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACK8 | ACK7 | ACK6 | ACK5 | ACK4 | ACK3 | ACK2 | ACK1 |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R-0 | 0h | Reserved |
11 | ACK12 | R/W1S | 0h | Acknowledge PIE Interrupt Group 12 Reset type: SYSRSn |
10 | ACK11 | R/W1S | 0h | Acknowledge PIE Interrupt Group 11 Reset type: SYSRSn |
9 | ACK10 | R/W1S | 0h | Acknowledge PIE Interrupt Group 10 Reset type: SYSRSn |
8 | ACK9 | R/W1S | 0h | Acknowledge PIE Interrupt Group 9 Reset type: SYSRSn |
7 | ACK8 | R/W1S | 0h | Acknowledge PIE Interrupt Group 8 Reset type: SYSRSn |
6 | ACK7 | R/W1S | 0h | Acknowledge PIE Interrupt Group 7 Reset type: SYSRSn |
5 | ACK6 | R/W1S | 0h | Acknowledge PIE Interrupt Group 6 Reset type: SYSRSn |
4 | ACK5 | R/W1S | 0h | Acknowledge PIE Interrupt Group 5 Reset type: SYSRSn |
3 | ACK4 | R/W1S | 0h | Acknowledge PIE Interrupt Group 4 Reset type: SYSRSn |
2 | ACK3 | R/W1S | 0h | Acknowledge PIE Interrupt Group 3 Reset type: SYSRSn |
1 | ACK2 | R/W1S | 0h | Acknowledge PIE Interrupt Group 2 Reset type: SYSRSn |
0 | ACK1 | R/W1S | 0h | Acknowledge PIE Interrupt Group 1 Reset type: SYSRSn |
PIEIER1 is shown in Figure 3-28 and described in Table 3-38.
Return to the Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 1.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 1.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 1.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 1.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 1.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 1.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 1.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 1.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 1.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 1.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 1.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 1.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 1.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 1.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 1.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 1.1 Reset type: SYSRSn |
PIEIFR1 is shown in Figure 3-29 and described in Table 3-39.
Return to the Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 1.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 1.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 1.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 1.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 1.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 1.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 1.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 1.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 1.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 1.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 1.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 1.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 1.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 1.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 1.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 1.1 Reset type: SYSRSn |
PIEIER2 is shown in Figure 3-30 and described in Table 3-40.
Return to the Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 2.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 2.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 2.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 2.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 2.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 2.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 2.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 2.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 2.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 2.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 2.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 2.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 2.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 2.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 2.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 2.1 Reset type: SYSRSn |
PIEIFR2 is shown in Figure 3-31 and described in Table 3-41.
Return to the Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 2.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 2.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 2.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 2.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 2.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 2.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 2.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 2.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 2.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 2.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 2.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 2.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 2.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 2.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 2.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 2.1 Reset type: SYSRSn |
PIEIER3 is shown in Figure 3-32 and described in Table 3-42.
Return to the Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 3.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 3.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 3.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 3.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 3.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 3.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 3.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 3.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 3.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 3.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 3.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 3.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 3.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 3.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 3.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 3.1 Reset type: SYSRSn |
PIEIFR3 is shown in Figure 3-33 and described in Table 3-43.
Return to the Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 3.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 3.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 3.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 3.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 3.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 3.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 3.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 3.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 3.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 3.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 3.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 3.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 3.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 3.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 3.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 3.1 Reset type: SYSRSn |
PIEIER4 is shown in Figure 3-34 and described in Table 3-44.
Return to the Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 4.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 4.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 4.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 4.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 4.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 4.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 4.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 4.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 4.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 4.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 4.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 4.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 4.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 4.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 4.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 4.1 Reset type: SYSRSn |
PIEIFR4 is shown in Figure 3-35 and described in Table 3-45.
Return to the Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 4.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 4.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 4.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 4.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 4.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 4.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 4.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 4.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 4.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 4.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 4.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 4.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 4.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 4.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 4.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 4.1 Reset type: SYSRSn |
PIEIER5 is shown in Figure 3-36 and described in Table 3-46.
Return to the Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 5.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 5.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 5.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 5.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 5.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 5.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 5.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 5.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 5.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 5.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 5.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 5.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 5.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 5.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 5.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 5.1 Reset type: SYSRSn |
PIEIFR5 is shown in Figure 3-37 and described in Table 3-47.
Return to the Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 5.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 5.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 5.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 5.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 5.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 5.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 5.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 5.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 5.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 5.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 5.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 5.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 5.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 5.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 5.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 5.1 Reset type: SYSRSn |
PIEIER6 is shown in Figure 3-38 and described in Table 3-48.
Return to the Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 6.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 6.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 6.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 6.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 6.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 6.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 6.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 6.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 6.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 6.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 6.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 6.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 6.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 6.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 6.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 6.1 Reset type: SYSRSn |
PIEIFR6 is shown in Figure 3-39 and described in Table 3-49.
Return to the Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 6.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 6.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 6.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 6.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 6.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 6.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 6.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 6.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 6.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 6.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 6.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 6.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 6.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 6.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 6.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 6.1 Reset type: SYSRSn |
PIEIER7 is shown in Figure 3-40 and described in Table 3-50.
Return to the Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 7.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 7.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 7.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 7.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 7.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 7.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 7.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 7.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 7.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 7.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 7.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 7.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 7.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 7.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 7.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 7.1 Reset type: SYSRSn |
PIEIFR7 is shown in Figure 3-41 and described in Table 3-51.
Return to the Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 7.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 7.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 7.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 7.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 7.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 7.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 7.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 7.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 7.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 7.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 7.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 7.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 7.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 7.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 7.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 7.1 Reset type: SYSRSn |
PIEIER8 is shown in Figure 3-42 and described in Table 3-52.
Return to the Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 8.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 8.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 8.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 8.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 8.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 8.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 8.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 8.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 8.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 8.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 8.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 8.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 8.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 8.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 8.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 8.1 Reset type: SYSRSn |
PIEIFR8 is shown in Figure 3-43 and described in Table 3-53.
Return to the Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 8.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 8.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 8.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 8.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 8.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 8.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 8.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 8.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 8.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 8.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 8.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 8.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 8.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 8.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 8.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 8.1 Reset type: SYSRSn |
PIEIER9 is shown in Figure 3-44 and described in Table 3-54.
Return to the Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 9.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 9.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 9.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 9.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 9.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 9.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 9.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 9.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 9.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 9.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 9.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 9.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 9.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 9.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 9.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 9.1 Reset type: SYSRSn |
PIEIFR9 is shown in Figure 3-45 and described in Table 3-55.
Return to the Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 9.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 9.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 9.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 9.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 9.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 9.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 9.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 9.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 9.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 9.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 9.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 9.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 9.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 9.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 9.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 9.1 Reset type: SYSRSn |
PIEIER10 is shown in Figure 3-46 and described in Table 3-56.
Return to the Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 10.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 10.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 10.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 10.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 10.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 10.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 10.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 10.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 10.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 10.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 10.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 10.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 10.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 10.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 10.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 10.1 Reset type: SYSRSn |
PIEIFR10 is shown in Figure 3-47 and described in Table 3-57.
Return to the Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 10.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 10.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 10.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 10.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 10.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 10.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 10.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 10.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 10.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 10.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 10.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 10.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 10.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 10.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 10.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 10.1 Reset type: SYSRSn |
PIEIER11 is shown in Figure 3-48 and described in Table 3-58.
Return to the Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 11.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 11.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 11.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 11.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 11.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 11.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 11.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 11.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 11.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 11.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 11.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 11.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 11.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 11.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 11.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 11.1 Reset type: SYSRSn |
PIEIFR11 is shown in Figure 3-49 and described in Table 3-59.
Return to the Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 11.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 11.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 11.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 11.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 11.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 11.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 11.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 11.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 11.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 11.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 11.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 11.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 11.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 11.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 11.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 11.1 Reset type: SYSRSn |
PIEIER12 is shown in Figure 3-50 and described in Table 3-60.
Return to the Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal can still set the PIEIFR bit for the disabled interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Enable for Interrupt 12.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Enable for Interrupt 12.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Enable for Interrupt 12.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Enable for Interrupt 12.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Enable for Interrupt 12.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Enable for Interrupt 12.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Enable for Interrupt 12.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Enable for Interrupt 12.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Enable for Interrupt 12.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Enable for Interrupt 12.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Enable for Interrupt 12.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Enable for Interrupt 12.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Enable for Interrupt 12.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Enable for Interrupt 12.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Enable for Interrupt 12.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Enable for Interrupt 12.1 Reset type: SYSRSn |
PIEIFR12 is shown in Figure 3-51 and described in Table 3-61.
Return to the Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution in the application code. Reading the PIE IFR registers is safe.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INTx16 | INTx15 | INTx14 | INTx13 | INTx12 | INTx11 | INTx10 | INTx9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTx8 | INTx7 | INTx6 | INTx5 | INTx4 | INTx3 | INTx2 | INTx1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | INTx16 | R/W | 0h | Flag for Interrupt 12.16 Reset type: SYSRSn |
14 | INTx15 | R/W | 0h | Flag for Interrupt 12.15 Reset type: SYSRSn |
13 | INTx14 | R/W | 0h | Flag for Interrupt 12.14 Reset type: SYSRSn |
12 | INTx13 | R/W | 0h | Flag for Interrupt 12.13 Reset type: SYSRSn |
11 | INTx12 | R/W | 0h | Flag for Interrupt 12.12 Reset type: SYSRSn |
10 | INTx11 | R/W | 0h | Flag for Interrupt 12.11 Reset type: SYSRSn |
9 | INTx10 | R/W | 0h | Flag for Interrupt 12.10 Reset type: SYSRSn |
8 | INTx9 | R/W | 0h | Flag for Interrupt 12.9 Reset type: SYSRSn |
7 | INTx8 | R/W | 0h | Flag for Interrupt 12.8 Reset type: SYSRSn |
6 | INTx7 | R/W | 0h | Flag for Interrupt 12.7 Reset type: SYSRSn |
5 | INTx6 | R/W | 0h | Flag for Interrupt 12.6 Reset type: SYSRSn |
4 | INTx5 | R/W | 0h | Flag for Interrupt 12.5 Reset type: SYSRSn |
3 | INTx4 | R/W | 0h | Flag for Interrupt 12.4 Reset type: SYSRSn |
2 | INTx3 | R/W | 0h | Flag for Interrupt 12.3 Reset type: SYSRSn |
1 | INTx2 | R/W | 0h | Flag for Interrupt 12.2 Reset type: SYSRSn |
0 | INTx1 | R/W | 0h | Flag for Interrupt 12.1 Reset type: SYSRSn |